Lines Matching refs:t7
36 #define t7 $15
109 move t7, zero
115 andi t7, src, 0x1 /* odd buffer? */
118 beqz t7, .Lword_align
287 movn sum, v1, t7
290 beqz t7, 1f /* odd buffer alignment? */
479 LOAD(t7, UNIT(7)(src))
495 ADDC(t6, t7)
496 STORE(t7, UNIT(7)(dst))
508 #define rem t7