Lines Matching refs:cop0
427 struct mips_coproc *cop0 = vcpu->arch.cop0;
430 compare = kvm_read_sw_gc0_compare(cop0);
431 cause = kvm_read_sw_gc0_cause(cop0);
522 struct mips_coproc *cop0 = vcpu->arch.cop0;
538 kvm_write_sw_gc0_cause(cop0, cause);
539 kvm_write_sw_gc0_compare(cop0, compare);
868 struct mips_coproc *cop0 = vcpu->arch.cop0;
872 kvm_write_sw_gc0_maari(cop0, ARRAY_SIZE(vcpu->arch.maar) - 1);
874 kvm_write_sw_gc0_maari(cop0, val);
881 struct mips_coproc *cop0 = vcpu->arch.cop0;
913 cop0->stat[rd][sel]++;
933 BUG_ON(kvm_read_sw_gc0_maari(cop0) >=
936 kvm_read_sw_gc0_maari(cop0)];
953 val = cop0->reg[rd][sel];
957 val = cop0->reg[rd][sel];
979 cop0->stat[rd][sel]++;
1012 BUG_ON(kvm_read_sw_gc0_maari(cop0) >=
1014 vcpu->arch.maar[kvm_read_sw_gc0_maari(cop0)] =
1023 cop0->reg[rd][sel] = (int)val;
1067 kvm_err("[%#lx]%s: unsupported cop0 instruction 0x%08x\n",
1910 struct mips_coproc *cop0 = vcpu->arch.cop0;
2031 *v = (long)kvm_read_c0_guest_prid(cop0);
2067 *v = kvm_read_sw_gc0_config6(cop0);
2080 *v = kvm_read_sw_gc0_maari(vcpu->arch.cop0);
2134 struct mips_coproc *cop0 = vcpu->arch.cop0;
2273 kvm_write_c0_guest_prid(cop0, v);
2339 cur = kvm_read_sw_gc0_config6(cop0);
2343 kvm_write_sw_gc0_config6(cop0, (int)v);
2561 struct mips_coproc *cop0 = vcpu->arch.cop0;
2581 kvm_restore_gc0_wired(cop0);
2609 kvm_restore_gc0_config(cop0);
2611 kvm_restore_gc0_config1(cop0);
2613 kvm_restore_gc0_config2(cop0);
2615 kvm_restore_gc0_config3(cop0);
2617 kvm_restore_gc0_config4(cop0);
2619 kvm_restore_gc0_config5(cop0);
2621 kvm_restore_gc0_config6(cop0);
2623 kvm_restore_gc0_config7(cop0);
2625 kvm_restore_gc0_index(cop0);
2626 kvm_restore_gc0_entrylo0(cop0);
2627 kvm_restore_gc0_entrylo1(cop0);
2628 kvm_restore_gc0_context(cop0);
2630 kvm_restore_gc0_contextconfig(cop0);
2632 kvm_restore_gc0_xcontext(cop0);
2634 kvm_restore_gc0_xcontextconfig(cop0);
2636 kvm_restore_gc0_pagemask(cop0);
2637 kvm_restore_gc0_pagegrain(cop0);
2638 kvm_restore_gc0_hwrena(cop0);
2639 kvm_restore_gc0_badvaddr(cop0);
2640 kvm_restore_gc0_entryhi(cop0);
2641 kvm_restore_gc0_status(cop0);
2642 kvm_restore_gc0_intctl(cop0);
2643 kvm_restore_gc0_epc(cop0);
2644 kvm_vz_write_gc0_ebase(kvm_read_sw_gc0_ebase(cop0));
2646 kvm_restore_gc0_userlocal(cop0);
2648 kvm_restore_gc0_errorepc(cop0);
2653 kvm_restore_gc0_kscratch1(cop0);
2655 kvm_restore_gc0_kscratch2(cop0);
2657 kvm_restore_gc0_kscratch3(cop0);
2659 kvm_restore_gc0_kscratch4(cop0);
2661 kvm_restore_gc0_kscratch5(cop0);
2663 kvm_restore_gc0_kscratch6(cop0);
2667 kvm_restore_gc0_badinstr(cop0);
2669 kvm_restore_gc0_badinstrp(cop0);
2672 kvm_restore_gc0_segctl0(cop0);
2673 kvm_restore_gc0_segctl1(cop0);
2674 kvm_restore_gc0_segctl2(cop0);
2679 kvm_restore_gc0_pwbase(cop0);
2680 kvm_restore_gc0_pwfield(cop0);
2681 kvm_restore_gc0_pwsize(cop0);
2682 kvm_restore_gc0_pwctl(cop0);
2688 cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL]);
2703 struct mips_coproc *cop0 = vcpu->arch.cop0;
2710 kvm_save_gc0_index(cop0);
2711 kvm_save_gc0_entrylo0(cop0);
2712 kvm_save_gc0_entrylo1(cop0);
2713 kvm_save_gc0_context(cop0);
2715 kvm_save_gc0_contextconfig(cop0);
2717 kvm_save_gc0_xcontext(cop0);
2719 kvm_save_gc0_xcontextconfig(cop0);
2721 kvm_save_gc0_pagemask(cop0);
2722 kvm_save_gc0_pagegrain(cop0);
2723 kvm_save_gc0_wired(cop0);
2726 kvm_save_gc0_hwrena(cop0);
2727 kvm_save_gc0_badvaddr(cop0);
2728 kvm_save_gc0_entryhi(cop0);
2729 kvm_save_gc0_status(cop0);
2730 kvm_save_gc0_intctl(cop0);
2731 kvm_save_gc0_epc(cop0);
2732 kvm_write_sw_gc0_ebase(cop0, kvm_vz_read_gc0_ebase());
2734 kvm_save_gc0_userlocal(cop0);
2737 kvm_save_gc0_config(cop0);
2739 kvm_save_gc0_config1(cop0);
2741 kvm_save_gc0_config2(cop0);
2743 kvm_save_gc0_config3(cop0);
2745 kvm_save_gc0_config4(cop0);
2747 kvm_save_gc0_config5(cop0);
2749 kvm_save_gc0_config6(cop0);
2751 kvm_save_gc0_config7(cop0);
2753 kvm_save_gc0_errorepc(cop0);
2758 kvm_save_gc0_kscratch1(cop0);
2760 kvm_save_gc0_kscratch2(cop0);
2762 kvm_save_gc0_kscratch3(cop0);
2764 kvm_save_gc0_kscratch4(cop0);
2766 kvm_save_gc0_kscratch5(cop0);
2768 kvm_save_gc0_kscratch6(cop0);
2772 kvm_save_gc0_badinstr(cop0);
2774 kvm_save_gc0_badinstrp(cop0);
2777 kvm_save_gc0_segctl0(cop0);
2778 kvm_save_gc0_segctl1(cop0);
2779 kvm_save_gc0_segctl2(cop0);
2784 kvm_read_sw_gc0_config3(cop0) & MIPS_CONF3_PW)) {
2785 kvm_save_gc0_pwbase(cop0);
2786 kvm_save_gc0_pwfield(cop0);
2787 kvm_save_gc0_pwsize(cop0);
2788 kvm_save_gc0_pwctl(cop0);
2795 cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] =
3075 struct mips_coproc *cop0 = vcpu->arch.cop0;
3092 kvm_write_sw_gc0_pagegrain(cop0, PG_RIE | PG_XIE | PG_IEC);
3095 kvm_write_sw_gc0_wired(cop0,
3098 kvm_write_sw_gc0_status(cop0, ST0_BEV | ST0_ERL);
3100 kvm_change_sw_gc0_status(cop0, ST0_FR, read_gc0_status());
3102 kvm_write_sw_gc0_intctl(cop0, read_gc0_intctl() &
3105 kvm_write_sw_gc0_prid(cop0, boot_cpu_data.processor_id);
3107 kvm_write_sw_gc0_ebase(cop0, (s32)0x80000000 | vcpu->vcpu_id);
3109 kvm_save_gc0_config(cop0);
3111 kvm_change_sw_gc0_config(cop0, CONF_CM_CMASK,
3114 kvm_change_sw_gc0_config(cop0, MIPS_CONF_MT, read_c0_config());
3116 kvm_set_sw_gc0_config(cop0, MIPS_CONF_M);
3118 kvm_save_gc0_config1(cop0);
3120 kvm_clear_sw_gc0_config1(cop0, MIPS_CONF1_C2 |
3128 kvm_set_sw_gc0_config1(cop0, MIPS_CONF_M);
3130 kvm_save_gc0_config2(cop0);
3133 kvm_set_sw_gc0_config2(cop0, MIPS_CONF_M);
3135 kvm_save_gc0_config3(cop0);
3137 kvm_clear_sw_gc0_config3(cop0, MIPS_CONF3_ISA_OE);
3139 kvm_clear_sw_gc0_config3(cop0, MIPS_CONF3_MSA |
3155 kvm_set_sw_gc0_config3(cop0, MIPS_CONF_M);
3157 kvm_save_gc0_config4(cop0);
3160 kvm_set_sw_gc0_config4(cop0, MIPS_CONF_M);
3162 kvm_save_gc0_config5(cop0);
3164 kvm_clear_sw_gc0_config5(cop0, MIPS_CONF5_K |
3172 kvm_clear_sw_gc0_config5(cop0, MIPS_CONF5_MRP);
3177 kvm_write_sw_gc0_contextconfig(cop0, 0x007ffff0);
3181 kvm_write_sw_gc0_xcontextconfig(cop0,
3189 kvm_write_sw_gc0_segctl0(cop0, 0x00200010);
3190 kvm_write_sw_gc0_segctl1(cop0, 0x00000002 |
3193 kvm_write_sw_gc0_segctl2(cop0, 0x00380438);
3199 kvm_write_sw_gc0_pwfield(cop0, 0x0c30c302);
3201 kvm_write_sw_gc0_pwsize(cop0, 1 << MIPS_PWSIZE_PTW_SHIFT);
3206 cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] = 0;