Lines Matching refs:K0
47 #define K0 26
258 UASM_i_LA(&p, K0, ST0_EXL | KSU_USER | ST0_BEV | ST0_KX_IF_64);
259 uasm_i_mtc0(&p, K0, C0_STATUS);
263 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, guest_ebase), K1);
264 build_set_exc_base(&p, K0);
271 uasm_i_addiu(&p, K0, ZERO, ST0_EXL | KSU_USER | ST0_IE | ST0_KX_IF_64);
273 uasm_i_or(&p, K0, K0, V0);
274 uasm_i_mtc0(&p, K0, C0_STATUS);
311 UASM_i_MFC0(&p, K0, C0_PWBASE);
313 UASM_i_MFC0(&p, K0, c0_kscratch(), pgd_reg);
314 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, host_pgd), K1);
337 uasm_i_mfc0(&p, K0, C0_GUESTCTL0);
338 uasm_i_ins(&p, K0, V1, MIPS_GCTL0_GM_SHIFT, 1);
339 uasm_i_mtc0(&p, K0, C0_GUESTCTL0);
363 UASM_i_MFC0(&p, K0, C0_ENTRYHI);
364 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, host_entryhi),
392 UASM_i_LW(&p, K0, 0, T3);
404 uasm_i_and(&p, K0, K0, T2);
406 uasm_i_andi(&p, K0, K0, MIPS_ENTRYHI_ASID);
421 uasm_i_mtc0(&p, K0, C0_ENTRYHI);
424 uasm_i_mtc0(&p, K0, C0_ENTRYHI);
435 if (i == K0 || i == K1)
442 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, hi), K1);
443 uasm_i_mthi(&p, K0);
445 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, lo), K1);
446 uasm_i_mtlo(&p, K0);
450 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, gprs[K0]), K1);
490 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu, arch.gprs[K0]), K1);
500 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */
502 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */
520 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
522 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
527 build_get_ptep(&p, K0, K1);
528 build_update_entries(&p, K0, K1);
538 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu, arch.gprs[K0]), K1);
577 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, gprs[K0]), K1);
625 if (i == K0 || i == K1)
653 UASM_i_MFC0(&p, K0, C0_EPC);
654 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, pc), K1);
656 UASM_i_MFC0(&p, K0, C0_BADVADDR);
657 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, host_cp0_badvaddr),
660 uasm_i_mfc0(&p, K0, C0_CAUSE);
661 uasm_i_sw(&p, K0, offsetof(struct kvm_vcpu_arch, host_cp0_cause), K1);
664 uasm_i_mfc0(&p, K0, C0_BADINSTR);
665 uasm_i_sw(&p, K0, offsetof(struct kvm_vcpu_arch,
670 uasm_i_mfc0(&p, K0, C0_BADINSTRP);
671 uasm_i_sw(&p, K0, offsetof(struct kvm_vcpu_arch,
682 uasm_i_or(&p, K0, V0, AT);
684 uasm_i_mtc0(&p, K0, C0_STATUS);
687 UASM_i_LA_mostly(&p, K0, (long)&ebase);
688 UASM_i_LW(&p, K0, uasm_rel_lo((long)&ebase), K0);
689 build_set_exc_base(&p, K0);
726 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, host_entryhi),
728 UASM_i_MTC0(&p, K0, C0_ENTRYHI);
748 uasm_i_mfc0(&p, K0, C0_GUESTCTL0);
749 uasm_i_ins(&p, K0, ZERO, MIPS_GCTL0_GM_SHIFT, 1);
750 uasm_i_mtc0(&p, K0, C0_GUESTCTL0);
753 uasm_i_sw(&p, K0,
795 kvm_mips_build_restore_scratch(&p, K0, SP);
798 UASM_i_LA_mostly(&p, K0, (long)&hwrena);
799 uasm_i_lw(&p, K0, uasm_rel_lo((long)&hwrena), K0);
800 uasm_i_mtc0(&p, K0, C0_HWRENA);
893 uasm_i_or(&p, K0, V1, AT);
894 uasm_i_mtc0(&p, K0, C0_STATUS);
933 uasm_i_sra(&p, K0, V0, 2);
934 uasm_i_move(&p, V0, K0);
944 UASM_i_LA_mostly(&p, K0, (long)&hwrena);
945 uasm_i_lw(&p, K0, uasm_rel_lo((long)&hwrena), K0);
946 uasm_i_mtc0(&p, K0, C0_HWRENA);