Lines Matching defs:counter
3 * Linux performance counter support for MIPS.
11 * counter access is based on the MIPS Oprofile code. And the callchain
36 * Set the bit (indexed by the counter number) when the counter
42 * Software copy of the control register for each performance counter.
209 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
229 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
289 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
321 * We only need to care the counter mask. The range has been
334 * when the former kind of event takes the counter the
335 * latter kind of event wants to use, then the "counter
368 /* enable the counter for the calling thread */
372 /* The counter is processor wide. Set it up to count all TCs. */
373 pr_debug("Enabling perf counter for all TCs\n");
379 * Set up the counter for a particular CPU when event->cpu is
380 * a valid CPU number. Otherwise set up the counter for the CPU
388 pr_debug("Enabling perf counter for CPU%d\n", cpu);
391 * We do not actually let the counter run. Leave it until start().
508 /* To look for a free counter for this event. */
516 * If there is an event in the counter we are going to use then
575 * counters on other CPUs alone. If any counter interrupt raises while
1567 * We allow max flexibility on how each individual counter shared
1589 * counter for it for now.
1644 u64 counter;
1670 counter = mipspmu.read_counter(n);
1671 if (!(counter & mipspmu.overflow))
1685 * in here because the performance counter interrupt is a regular