Lines Matching refs:did
242 * Address for new work request loads (did<2:0> == 0)
252 /* the ID of POW -- did<2:0> == 0 in this case */
253 uint64_t did:8;
267 uint64_t did:8;
285 /* the ID of POW -- did<2:0> == 1 in this case */
286 uint64_t did:8;
315 uint64_t did:8;
333 /* the ID of POW -- did<2:0> == 2 in this case */
334 uint64_t did:8;
359 uint64_t did:8;
377 /* the ID of POW -- did<2:0> == 3 in this case */
378 uint64_t did:8;
423 uint64_t did:8;
431 * address for NULL_RD request (did<2:0> == 4) when this is read,
446 /* the ID of POW -- did<2:0> == 4 in this case */
447 uint64_t did:8;
452 uint64_t did:8;
1174 * for POW stores (i.e. when did<7:3> == 0xc)
1175 * - did<2:0> == 0 => pending switch bit is set
1176 * - did<2:0> == 1 => no affect on the pending switch bit
1177 * - did<2:0> == 3 => pending switch bit is cleared
1178 * - did<2:0> == 7 => no affect on the pending switch bit
1179 * - did<2:0> == others => must not be used
1183 * NOTE: did<2:0> == 2 is used by the HW for a special single-cycle
1185 * did<2:0> == 2.
1200 uint64_t did:8;
1207 uint64_t did:8;
1231 uint64_t did:8;
1240 uint64_t did:8;
1268 load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
1294 load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
1363 ptr.swork.did = CVMX_OCT_DID_TAG_SWTAG;
1417 ptr.snull_rd.did = CVMX_OCT_DID_TAG_NULL_RD;
1449 data.s.did = CVMX_OCT_DID_TAG_SWTAG;
1573 ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG;
1685 ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG;
1762 ptr.sio.did = CVMX_OCT_DID_TAG_TAG1;
1829 ptr.sio.did = CVMX_OCT_DID_TAG_TAG1;
1986 ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;
2086 ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;