Lines Matching refs:reg
123 * @reg: FAU atomic register to access. 0 <= reg < 2048.
129 static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg)
133 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
143 * @reg: FAU atomic register to access. 0 <= reg < 2048.
152 static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg,
158 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
164 * @reg: FAU atomic register to access. 0 <= reg < 2048.
170 static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg,
173 return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value));
179 * @reg: FAU atomic register to access. 0 <= reg < 2048.
185 static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
188 reg ^= SWIZZLE_32;
189 return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value));
195 * @reg: FAU atomic register to access. 0 <= reg < 2048.
200 static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg,
203 reg ^= SWIZZLE_16;
204 return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value));
210 * @reg: FAU atomic register to access. 0 <= reg < 2048.
214 static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
216 reg ^= SWIZZLE_8;
217 return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value));
224 * @reg: FAU atomic register to access. 0 <= reg < 2048.
233 cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value)
240 cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value));
248 * @reg: FAU atomic register to access. 0 <= reg < 2048.
257 cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
263 reg ^= SWIZZLE_32;
265 cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value));
273 * @reg: FAU atomic register to access. 0 <= reg < 2048.
281 cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
287 reg ^= SWIZZLE_16;
289 cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value));
297 * @reg: FAU atomic register to access. 0 <= reg < 2048.
304 cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
310 reg ^= SWIZZLE_8;
311 result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value));
331 * @reg: FAU atomic register to access. 0 <= reg < 2048.
340 uint64_t reg)
348 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
357 * @reg: FAU atomic register to access. 0 <= reg < 2048.
364 cvmx_fau_reg_64_t reg,
368 (scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg));
377 * @reg: FAU atomic register to access. 0 <= reg < 2048.
384 cvmx_fau_reg_32_t reg,
388 (scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg));
397 * @reg: FAU atomic register to access. 0 <= reg < 2048.
403 cvmx_fau_reg_16_t reg,
407 (scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg));
416 * @reg: FAU atomic register to access. 0 <= reg < 2048.
421 cvmx_fau_reg_8_t reg,
425 (scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg));
437 * @reg: FAU atomic register to access. 0 <= reg < 2048.
444 cvmx_fau_reg_64_t reg,
448 (scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg));
460 * @reg: FAU atomic register to access. 0 <= reg < 2048.
467 cvmx_fau_reg_32_t reg,
471 (scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg));
483 * @reg: FAU atomic register to access. 0 <= reg < 2048.
490 cvmx_fau_reg_16_t reg,
494 (scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg));
506 * @reg: FAU atomic register to access. 0 <= reg < 2048.
512 cvmx_fau_reg_8_t reg,
516 (scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg));
522 * @reg: FAU atomic register to access. 0 <= reg < 2048.
526 static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)
528 cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value);
534 * @reg: FAU atomic register to access. 0 <= reg < 2048.
538 static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
540 reg ^= SWIZZLE_32;
541 cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value);
547 * @reg: FAU atomic register to access. 0 <= reg < 2048.
551 static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
553 reg ^= SWIZZLE_16;
554 cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value);
560 * @reg: FAU atomic register to access. 0 <= reg < 2048.
563 static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value)
565 reg ^= SWIZZLE_8;
566 cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value);
572 * @reg: FAU atomic register to access. 0 <= reg < 2048.
576 static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)
578 cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value);
584 * @reg: FAU atomic register to access. 0 <= reg < 2048.
588 static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
590 reg ^= SWIZZLE_32;
591 cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value);
597 * @reg: FAU atomic register to access. 0 <= reg < 2048.
601 static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
603 reg ^= SWIZZLE_16;
604 cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value);
610 * @reg: FAU atomic register to access. 0 <= reg < 2048.
613 static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value)
615 reg ^= SWIZZLE_8;
616 cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value);