Lines Matching refs:BIT_ULL
366 #define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
367 #define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
368 #define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
369 #define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
370 #define MIPS_CPU_TX39_CACHE BIT_ULL( 4) /* TX3900-style caches */
371 #define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
372 #define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
373 #define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
374 #define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */
375 #define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */
376 #define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */
377 #define MIPS_CPU_CACHE_CDEX_P BIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
378 #define MIPS_CPU_CACHE_CDEX_S BIT_ULL(12) /* ... same for seconary cache ... */
379 #define MIPS_CPU_MCHECK BIT_ULL(13) /* Machine check exception */
380 #define MIPS_CPU_EJTAG BIT_ULL(14) /* EJTAG exception */
381 #define MIPS_CPU_NOFPUEX BIT_ULL(15) /* no FPU exception */
382 #define MIPS_CPU_LLSC BIT_ULL(16) /* CPU has ll/sc instructions */
383 #define MIPS_CPU_INCLUSIVE_CACHES BIT_ULL(17) /* P-cache subset enforced */
384 #define MIPS_CPU_PREFETCH BIT_ULL(18) /* CPU has usable prefetch */
385 #define MIPS_CPU_VINT BIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
386 #define MIPS_CPU_VEIC BIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
387 #define MIPS_CPU_ULRI BIT_ULL(21) /* CPU has ULRI feature */
388 #define MIPS_CPU_PCI BIT_ULL(22) /* CPU has Perf Ctr Int indicator */
389 #define MIPS_CPU_RIXI BIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
390 #define MIPS_CPU_MICROMIPS BIT_ULL(24) /* CPU has microMIPS capability */
391 #define MIPS_CPU_TLBINV BIT_ULL(25) /* CPU supports TLBINV/F */
392 #define MIPS_CPU_SEGMENTS BIT_ULL(26) /* CPU supports Segmentation Control registers */
393 #define MIPS_CPU_EVA BIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
394 #define MIPS_CPU_HTW BIT_ULL(28) /* CPU support Hardware Page Table Walker */
395 #define MIPS_CPU_RIXIEX BIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
396 #define MIPS_CPU_MAAR BIT_ULL(30) /* MAAR(I) registers are present */
397 #define MIPS_CPU_FRE BIT_ULL(31) /* FRE & UFE bits implemented */
398 #define MIPS_CPU_RW_LLB BIT_ULL(32) /* LLADDR/LLB writes are allowed */
399 #define MIPS_CPU_LPA BIT_ULL(33) /* CPU supports Large Physical Addressing */
400 #define MIPS_CPU_CDMM BIT_ULL(34) /* CPU has Common Device Memory Map */
401 #define MIPS_CPU_SP BIT_ULL(36) /* Small (1KB) page support */
402 #define MIPS_CPU_FTLB BIT_ULL(37) /* CPU has Fixed-page-size TLB */
403 #define MIPS_CPU_NAN_LEGACY BIT_ULL(38) /* Legacy NaN implemented */
404 #define MIPS_CPU_NAN_2008 BIT_ULL(39) /* 2008 NaN implemented */
405 #define MIPS_CPU_VP BIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
406 #define MIPS_CPU_LDPTE BIT_ULL(41) /* CPU has ldpte/lddir instructions */
407 #define MIPS_CPU_MVH BIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
408 #define MIPS_CPU_EBASE_WG BIT_ULL(43) /* CPU has EBase.WG */
409 #define MIPS_CPU_BADINSTR BIT_ULL(44) /* CPU has BadInstr register */
410 #define MIPS_CPU_BADINSTRP BIT_ULL(45) /* CPU has BadInstrP register */
411 #define MIPS_CPU_CTXTC BIT_ULL(46) /* CPU has [X]ConfigContext registers */
412 #define MIPS_CPU_PERF BIT_ULL(47) /* CPU has MIPS performance counters */
413 #define MIPS_CPU_GUESTCTL0EXT BIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
414 #define MIPS_CPU_GUESTCTL1 BIT_ULL(49) /* CPU has VZ GuestCtl1 register */
415 #define MIPS_CPU_GUESTCTL2 BIT_ULL(50) /* CPU has VZ GuestCtl2 register */
416 #define MIPS_CPU_GUESTID BIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
417 #define MIPS_CPU_DRG BIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
418 #define MIPS_CPU_UFR BIT_ULL(53) /* CPU supports User mode FR switching */
420 BIT_ULL(54) /* CPU shares FTLB RAM with another */
422 BIT_ULL(55) /* CPU shares FTLB entries with another */
424 BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
425 #define MIPS_CPU_MMID BIT_ULL(57) /* CPU supports MemoryMapIDs */
426 #define MIPS_CPU_MM_SYSAD BIT_ULL(58) /* CPU supports write-through SysAD Valid merge */
427 #define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */
428 #define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */
429 #define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */
430 #define MIPS_CPU_GSEXCEX BIT_ULL(62) /* CPU has GSExc exception */