Lines Matching refs:reg
56 void ath79_ddr_wb_flush(u32 reg)
58 void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4);
90 u32 reg;
94 reg = AR71XX_RESET_REG_RESET_MODULE;
96 reg = AR724X_RESET_REG_RESET_MODULE;
98 reg = AR913X_RESET_REG_RESET_MODULE;
100 reg = AR933X_RESET_REG_RESET_MODULE;
102 reg = AR934X_RESET_REG_RESET_MODULE;
104 reg = QCA953X_RESET_REG_RESET_MODULE;
106 reg = QCA955X_RESET_REG_RESET_MODULE;
108 reg = QCA956X_RESET_REG_RESET_MODULE;
113 t = ath79_reset_rr(reg);
114 ath79_reset_wr(reg, t | mask);
122 u32 reg;
126 reg = AR71XX_RESET_REG_RESET_MODULE;
128 reg = AR724X_RESET_REG_RESET_MODULE;
130 reg = AR913X_RESET_REG_RESET_MODULE;
132 reg = AR933X_RESET_REG_RESET_MODULE;
134 reg = AR934X_RESET_REG_RESET_MODULE;
136 reg = QCA953X_RESET_REG_RESET_MODULE;
138 reg = QCA955X_RESET_REG_RESET_MODULE;
140 reg = QCA956X_RESET_REG_RESET_MODULE;
145 t = ath79_reset_rr(reg);
146 ath79_reset_wr(reg, t & ~mask);