Lines Matching refs:set
107 move.l %d1,(%a0)+ | set sign / exp
108 move.l %d0,(%a0)+ | set mantissa
138 bset #31,%d0 | set explizit bit
176 bset #31,%d0 | set explizit bit
221 | The high bit is set, so normalization is irrelevant.
446 | The high bit is set, so normalization is irrelevant.
695 clr.w %d2 | first set z bit, addx only clears it
698 | bit is set, then the number is odd, so rounding works like
737 | Exponent underflow. Try to make a denormal, and set it to
740 fp_set_sr FPSR_EXC_UNFL | set UNFL bit
761 bset #0,%d0 | Yes, so set the "sticky bit".
902 | is now zero. We will set the mantissa to reflect this, and
923 | Exponent underflow. Try to make a denormal, and set it to
926 fp_set_sr FPSR_EXC_UNFL | set UNFL bit
1062 | is now zero. We will set the mantissa to reflect this, and
1134 .set inf,(1<<(\b-1))-1 | i.e. MAXINT
1217 fp_clr_sr FPSR_EXC_UNFL | fp_normalize_ext has set this bit
1248 | fp_normalize_ext has set this bit already
1351 | set the emulated status register based on the outcome of an
1394 9: move.b %d0,(FPD_FPSR+0,FPDATA) | set condition test result
1396 | Here, we test things in the exception status byte, and set
1398 | Emulated instructions can set various things in the former,
1407 1: bset #FPSR_AEXC_IOP,%d0 | set IOP bit
1410 bset #FPSR_AEXC_OVFL,%d0 | set OVFL bit
1415 bset #FPSR_AEXC_UNFL,%d0 | set UNFL bit
1418 bset #FPSR_AEXC_DZ,%d0 | set DZ bit
1425 1: bset #FPSR_AEXC_INEX,%d0 | set INEX bit