Lines Matching defs:via2
41 volatile __u8 *via1, *via2;
117 via2 = NULL;
125 via2 = (void *)RBV_BASE;
126 pr_debug("VIA2 (RBV) detected at %p\n", via2);
146 via2 = (void *) VIA2_BASE;
147 pr_debug("VIA2 detected at %p\n", via2);
225 via2[gIER] = 0x7F;
226 via2[gIFR] = 0x7F | rbv_clear;
228 via2[vT1LL] = 0;
229 via2[vT1LH] = 0;
230 via2[vT1CL] = 0;
231 via2[vT1CH] = 0;
232 via2[vT2CL] = 0;
233 via2[vT2CH] = 0;
234 via2[vACR] &= ~0xC0; /* setup T1 timer with no PB7 output */
235 via2[vACR] &= ~0x03; /* disable port A & B latches */
255 pr_debug("VIA2 vPCR is 0x%02X\n", via2[vPCR]);
258 via2[vPCR] = 0x66;
261 via2[vPCR] = 0x22;
275 if (!via2)
279 (uint) via2[rIFR], (uint) via2[rIER]);
281 (uint) via2[rSIFR], (uint) via2[rSIER]);
284 (uint) via2[vDirA], (uint) via2[vDirB],
285 (uint) via2[vACR]);
287 (uint) via2[vPCR],
288 (uint) via2[vIFR], (uint) via2[vIER]);
302 via2[gBufB] &= ~VIA2B_vMode32;
303 via2[gBufB] |= VIA2B_vMode32;
314 if (!via2) {
319 return (int) via2[gBufB] & VIA2B_vCDis;
334 via2[vDirB] |= 0x02;
338 via2[gBufB] |= 0x02;
349 pr_debug("VIA2 vDirA is 0x%02X\n", via2[vDirA]);
353 via2[rSIER] = 0x7F;
368 via2[vDirA] &= 0xC0 | ~(1 << irq_idx);
371 via2[vDirA] &= 0x80 | ~(1 << irq_idx);
442 events = via2[gIFR] & via2[gIER] & 0x7F;
450 via2[gIFR] = irq_bit | rbv_clear;
468 events = ~via2[gBufA] & 0x7F;
470 events &= via2[rSIER];
472 events &= ~via2[vDirA];
489 via2[gIFR] = 0x02 | rbv_clear;
490 events = ~via2[gBufA] & 0x7F;
492 events &= via2[rSIER];
494 events &= ~via2[vDirA];
524 via2[gIER] = IER_SET_BIT(irq_idx);
532 via2[gIER] = IER_SET_BIT(1);
538 via2[rSIER] = IER_SET_BIT(irq_idx);
551 via2[gIER] = IER_CLR_BIT(irq_idx);
558 via2[gIER] = IER_CLR_BIT(1);
561 via2[rSIER] = IER_CLR_BIT(irq_idx);
578 return via2[gIFR] & (1 << IRQ_IDX(IRQ_MAC_SCSIDRQ));