Lines Matching defs:and
9 THE SOFTWARE is provided on an "AS IS" basis and without warranty.
13 and any warranty against infringement with regard to the SOFTWARE
14 (INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
21 Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
23 You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
24 so long as this entire notice is retained without alteration in any modified and/or
25 redistributed versions, and that such modified versions are clearly identified as such.
31 # and contains the entry points into the package. The user, in
39 # it makes the FPSP code easier to read and more mainatinable.
491 set nzi_mask, 0x01ffffff #clears N, Z, and I
620 # exceptional operand and plave it in the fsave state frame, and store #
630 # overflow was disabled and the trace exception was enabled, this #
664 # since, I believe, only NORMs and DENORMs can come through here,
670 # bit five of the fp extension word separates the monadic and dyadic operations
671 # that can pass through fpsp_ovfl(). remember that fcmp, ftst, and fsincos
722 # and inexact. and, the inexact is such that overflow occurred and was disabled
788 and.l &0xffff00ff,USER_FPSR(%a6) # zero all but accured field
860 # exceptional operand and plave it in the fsave state frame, and store #
866 # but the inexact exception was enabled and the result was inexact, #
870 # underflow was disabled and the trace exception was enabled, this #
908 # bit five of the fp ext word separates the monadic and dyadic operations
909 # that can pass through fpsp_unfl(). remember that fcmp, and ftst
970 # and inexact. and, the inexact is such that overflow occurred and was disabled
1062 and.l &0xffff00ff,USER_FPSR(%a6) # zero all but accured field
1142 # instructions, and (2) PACKED unimplemented data format instructions #
1144 # For UNNORM/DENORM opclass 0 and 2, the handler fetches the src #
1145 # operand from the fsave state frame and the dst operand (if dyadic) #
1148 # instruction type. Once the instruction has been emulated and result #
1152 # this exception into the FPU in the fsave state frame and then exit #
1154 # PACKED opclass 0 and 2 is similar in how the instruction is #
1155 # emulated and exceptions handled. The differences occur in how the #
1156 # handler loads the packed op (by calling get_packed() routine) and #
1159 # frame is changed to a Trace exception stack frame and an exit is #
1167 # type and jump to either _real_snan(), _real_operr(), _real_inex(), #
1174 # (1) DENORM and UNNORM (unimplemented) data types:
1189 # (2) PACKED format (unsupported) opclasses two and three:
1235 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD
1242 # stack frame and protocol.
1260 # precision format if the src format was single or double and the
1279 # bit five of the fp extension word separates the monadic and dyadic operations
1326 # fcmp and ftst do not store any result.
1346 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled
1369 # An exception occurred and that exception was enabled:
1425 # If the input operand to this operation was opclass two and a single
1494 # the src operand is in FP_SRC. Call _fout() to write out the result and
1498 # Separate packed move outs from the UNNORM and DENORM move outs.
1509 and.l &0xffff00ff,USER_FPSR(%a6) # zero exception field
1615 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled
1620 # if a disabled overflow occurred and inexact was enabled but the result
1633 # from FPIAR and put it in the trace stack frame then jump to _real_trace().
1653 # an exception occurred and that exception was enabled.
1657 # we don't mess with the existing fsave frame. just re-insert it and
1723 # exception occurred from user mode, then simply update a7 and exit normally.
1785 # fmove in and out enter here.
1824 # bit five of the fp extension word separates the monadic and dyadic operations
1871 # fcmp and ftst do not store any result.
1924 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled & set
1947 # An exception occurred and that exception was enabled:
1975 # as a reminder for future predicted pain and agony, we are passing in fsave the
1976 # "non-skewed" operand for cases of sgl and dbl src INFs,NANs, and DENORMs.
2039 # exception was being traced. Make the "current" PC the FPIAR and put it in the
2068 and.l &0xffff00ff,USER_FPSR(%a6) # zero exception field
2160 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled
2166 # an exception occurred and that exception was enabled.
2167 # the only exception possible on packed move out are INEX, OPERR, and SNAN.
2408 # _mem_read() "callout", converted to FP binary (if packed), and used #
2411 # emulation, then the result is stored to the destination register and #
2421 # decode and emulate the instruction. No FP exceptions can be pending #
2424 # to a Trace stack frame and an exit made through _real_trace(). #
2431 # Again, a Trace exception may be pending and an exit made through #
2446 # frame. This information includes a faulting address and a fault- #
2456 # So, we must check to see if it's disabled and handle that case separately.
2475 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD
2583 # now, we're left with ftst and fcmp. so, first let's tag them so that they don't
2584 # store a result. then, only fcmp will branch back and pick up a dst operand.
2648 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enable and set
2711 # exception was being traced. Make the "current" PC the FPIAR and put it in
2803 # right now, d1 = size and d0 = the strg.
2943 # The FPU is disabled and so we should really have taken the "Line
2961 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD
2981 # modes and thus can have several different total instruction lengths.
2982 # call fmovm_calc_ea which will go through the ea calc process and,
3090 # for opclass zero and two instruction taking this exception, the #
3092 # and needs to be corrected. This handler calls fix_skewed_ops() to #
3093 # do just this and then exits through _real_operr(). #
3154 # byte, word, and long destination format operations can pass
3156 # operand and save the appropriate minimum or maximum integer value
3280 # for opclass zero and two instructions taking this exception, the #
3282 # and needs to be corrected. This handler calls fix_skewed_ops() to #
3283 # do just this and then exits through _real_snan(). #
3328 # denorm operand in the sgl or dbl format. NANs also become skewed and must be
3350 # byte, word, long, and packed destination format operations can pass
3353 # for byte, word, and long, we simply need to test the sign of the src
3354 # operand and save the appropriate minimum or maximum integer value
3581 # for opclass zero and two instruction taking this exception, the #
3583 # register as did the '040 and '881/2. This handler must emulate the #
3584 # instruction in order to get this value and then store it to the #
3618 # the hardware, for "fabs" and "fneg" w/ a long source format, puts the
3634 # Here, we zero the ccode and exception byte field since we're going to
3652 # bits four and five of the fp extension word separate the monadic and dyadic
3653 # operations that can pass through fpsp_inex(). remember that fcmp and ftst
3715 # byte, word, and long destination format operations can pass
3716 # through here. so can double and single precision.
3761 # be incorrect for some cases and need to be adjusted. So, this package #
3762 # adjusts the operand using fix_skewed_ops() and then branches to #
3831 # classifed as "Line F". This module determines which case exists and #
3862 # The stacked <ea> for FP unimplemented instructions and opclass #
3866 # Also, for extended precision and packed, the #
3870 # stacked b,w,l and s sizes are completely stacked. #
3871 # d,x, and p are not. #
3915 # the <ea> is stacked correctly for all but extended and packed which
3936 # and packed data opclass 3 operations. #
3948 # For opclass 3 extended and packed data operations, the <ea> #
3949 # stacked for the exception is incorrect for -(an) and (an)+ addressing #
3953 # and return that value as the correct <ea> and store that value in An. #
3959 # for fmove outs of type extended and packed.
3977 # (An)+ : extended and packed fmove out
4022 # -(An) : extended and packed fmove out
4230 # The data register is determined and its value loaded to get the #
4235 # to read in all FP values. Again, _mem_read() may fail and require a #
4240 # then we return the size of the dump and the string to the caller #
4285 # but, make sure that we've calculated ea and advanced the opword pointer
4302 # operations and postincrement mode. (bit7 = FP7 ... bit0 = FP0)
4315 # we're also passing "size" and "strg" back to the calling routine
4575 # currently, MODE and REG are taken from the EXC_OPWORD. this could be
5403 # equal to 0x3fff and scale the SRC exponent by the value that the #
5454 and.w &0x8000,%d1
5523 # of the difference between the original and new exponent. Then, #
5577 # to 0x3ffe and return a scale factor of "(exp-0x3ffe)/2". If the #
5578 # exponent of the input operand is off, set the exponent to ox3fff and #
5650 # of the difference between the original and new exponent. Then, #
5709 # enable bit is set in the FPCR, then the trap is taken and the #
5712 # SNAN bit in the operand to one), and the operation continues as #
5816 # mantissa bits right, maintain the value of the guard, round, and #
5835 # Load the exponent threshold for the precision selected and check
5837 # simply calculate the sticky bit and zero the mantissa. otherwise
5858 # calculate if the sticky should be set and clear the entire mantissa.
5887 # make a copy of FTEMP_LO and place the g,r,s bits directly after it
5961 and.l &0xe0000000, %d0 # clear all but G,R,S
5992 subi.w &0x20, %d1 # %d1 now between 0 and 32
6020 and.l &0xe0000000, %d0 # clear all but G,R,S
6041 # Shift value is > 65 and out of range. All bits are shifted off.
6072 and.l &0xc0000000, %d0 # extract G,R
6073 and.l &0x3fffffff, %d1 # extract other bits
6099 and.l &0x80000000, %d0 # extract R bit
6101 and.l &0x7fffffff, %d1 # extract other bits
6104 # last operation done was an "and" of the bits shifted off so the condition
6114 # the guard and
6156 # a0 is preserved and the g-r-s bits in d0 are cleared. #
6168 # ext_grs() looks at the rounding precision and sets the appropriate
6170 # If (G,R,S == 0) then result is exact and round is done, else set
6171 # the inex flag in status reg and continue.
6230 # If (g=1), then add 1 to l and if (r=s=0), then clear l #
6256 add.w &0x1, FTEMP_EX(%a0) # and incr exponent
6260 and.w &0xfe00, FTEMP_HI+2(%a0) # clear the l-bit
6262 and.l &0xffffff00, FTEMP_HI(%a0) # truncate bits beyond sgl limit
6278 add.w &0x1,FTEMP_EX(%a0) # and inc exp
6282 and.b &0xfe,FTEMP_LO+3(%a0) # clear the l bit
6303 and.w &0xf000, FTEMP_LO+2(%a0) # clear the l-bit
6306 and.l &0xfffff800,FTEMP_LO(%a0) # truncate bits beyond dbl limit
6322 # ext_grs(): extract guard, round and sticky bits according to
6336 # Notes: the ext_grs uses the round PREC, and therefore has to swap d1
6337 # prior to usage, and needs to restore d1 to original. this
6338 # routine is tightly tied to the round routine and not meant to
6378 and.l &0x0000003f, %d2 # s bit is the or of all other
6384 bra.b ext_grs_end_sd # if words 3 and 4 are clr, exit
6403 and.l &0x000001ff, %d2 # s bit is the or-ing of all
6497 # zero; both the exponent and mantissa are changed. #
6521 and.w &0x7fff, %d1 # strip off sgn
6531 and.w &0x8000, %d0 # save old sign
6554 and.w &0x8000, FTEMP_EX(%a0) # set exp = 0
6571 and.w &0x8000, FTEMP_EX(%a0) # set exp = 0
6580 and.w &0x8000, FTEMP_EX(%a0) # force exponent to zero
6600 # Simply test the exponent, j-bit, and mantissa values to #
6602 # If it's an unnormalized zero, alter the operand and force it #
6651 and.l &0x7fffffff, %d0 # msb is a don't care!
6680 # Simply test the exponent, j-bit, and mantissa values to #
6700 and.l &0x000fffff, %d1
6711 and.l &0x000fffff, %d1
6743 # Simply test the exponent, j-bit, and mantissa values to #
6763 and.l &0x007fffff, %d1
6772 and.l &0x007fffff, %d1
6793 # single round prec and extended prec mode. #
6810 # exponent is extended to 16 bits and the sign is stored in the unused #
6818 # precision and the rounding mode to single. #
6829 and.w &0x7fff, %d1
6872 # can inex1 also be set along with unfl and inex2???
6884 # unf_res() for fsglmul() and fsgldiv().
6893 and.w &0x7fff,%d1
6932 # can inex1 also be set along with unfl and inex2???
6968 # the result and the rounding mode/prec in effect. These bits are #
6987 and.w &0x10, %d1 # keep result sign
6995 # use the rounding mode, precision, and result sign as in index into the
6996 # two tables below to fetch the default result and the result ccodes.
7085 # either occurs and is enabled, the EXOP. #
7088 # the source is a denorm and if underflow is enabled, an EXOP must be #
7283 # the stack frame. so, leave it in FP_SRC for now and deal with it later...
7342 # separately. otherwise, set the FPCR to the proper rounding mode and
7364 fmov.s %fp0,%d0 # store does convert and round
7392 # so, denorm and round and then use generic store single routine to
7459 # call ovf_res() w/ sgl prec and the correct rnd mode to create the default
7580 # separately. otherwise, set the FPCR to the proper rounding mode and
7602 fmov.d %fp0,L_SCR1(%a6) # store does convert and round
7621 # so, denorm and round and then use generic store double routine to
7680 # call ovf_res() w/ dbl prec and the correct rnd mode to create the default
7850 lsr.l &0x8,%d1 # and put them flush right
7976 # Handle NANs, infinities, and zeroes as special cases. Divide #
7982 # and return the EXOP if exceptions are enabled. Else, scale the #
8048 # - do the multiply to the proper precision and rounding mode.
8083 # - do the multiply to the proper precision and rounding mode in order to
8085 # - calculate the default result and return it in fp0.
8089 # multiply using extended precision and the correct rounding mode. the result
8167 # - do the multiply to the proper precision and rounding mode in order to
8169 # - calculate the default result and return it in fp0.
8194 # - do the multiply to the proper precision and rounding mode in order to
8196 # - calculate the default result and return it in fp0.
8200 # multiply using extended precision and the correct rounding mode. the result
8280 # -use the correct rounding mode and precision. this code favors operations
8471 # Handle NANs, infinities, and zeroes as special cases. Divide #
8472 # norms into extended, single, and double precision. #
8474 # sgl/dbl, must scale exponent and perform an "fmove". Check to see #
8501 # FP MOVE IN: NORMs and DENORMs ONLY!
8510 # skip the scaling and unscaling...
8538 # the input is an extended DENORM and underflow is enabled in the FPCR.
8539 # normalize the mantissa and add the bias of 0x6000 to the resulting negative
8540 # exponent and insert back into the operand.
8707 # now, round to extended(and don't alter the FPSR).
8748 # operand is not a NORM: check its optype and branch accordingly
8759 # do the fmove in; at this point, only possible ops are ZERO and INF.
8793 # Handle NANs, infinities, and zeroes as special cases. Divide #
8799 # and return the EXOP if exceptions are enabled. Else, scale the #
8838 # DIVIDE: NORMs and DENORMs ONLY!
9179 # The destination was In Range and the source was a ZERO. The result,
9181 # So, determine the sign and return a new INF (w/ the j-bit cleared).
9246 # Handle NANs, zeroes, and infinities as special cases. Separate #
9249 # and an actual fneg performed to see if overflow/underflow would have #
9251 # scale the result exponent and return result. FPSR gets set based on #
9274 # NEGATE SIGN : norms and denorms ONLY!
9283 # skip the scaling and unscaling...
9321 # the input is an extended DENORM and underflow is enabled in the FPCR.
9322 # normalize the mantissa and add the bias of 0x6000 to the resulting negative
9323 # exponent and insert back into the operand.
9487 # now, round to extended(and don't alter the FPSR).
9539 # do the fneg; at this point, only possible ops are ZERO and INF.
9563 # Check the source operand tag (STAG) and set the FPCR according #
9564 # to the operand type and sign. #
9652 # For denorms, force the j-bit to a one and do the same as for #
9700 # also, the INEX2 and AINEX exception bits will be set.
9702 # to a very small NORM and ship it to the NORM routine.
9758 # For denorms, force the j-bit to a one and do the same as for #
9802 # also, the INEX2 and AINEX exception bits will be set.
9804 # to a very small NORM and ship it to the NORM routine.
9864 # Handle NANs, infinities, and zeroes as special cases. Divide #
9865 # norms into extended, single, and double precision. #
9868 # Double and single precision can overflow and underflow. First, #
9874 # result exponent and return. #
9897 # ABSOLUTE VALUE: norms and denorms ONLY!
9906 # skip the scaling and unscaling...
9939 # the input is an extended DENORM and underflow is enabled in the FPCR.
9940 # normalize the mantissa and add the bias of 0x6000 to the resulting negative
9941 # exponent and insert back into the operand.
10102 # now, round to extended(and don't alter the FPSR).
10181 # Handle NANs and denorms as special cases. For everything else, #
10196 # COMPARE FP OPs : NORMs, ZEROs, INFs, and "corrected" DENORMs
10272 # unlike all other functions for QNAN and SNAN, fcmp does NOT set the
10286 # and use the fcmp_norm routine.
10287 # If you have a DENORM and an INF or ZERO, just force the DENORM's j-bit to a one
10288 # and use the fcmp_norm routine.
10289 # If you have a DENORM and a NORM with opposite signs, then use fcmp_norm, also.
10290 # But with a DENORM and a NORM of the same sign, the neg bit is set if the
10291 # (1) signs are (+) and the DENORM is the dst or
10292 # (2) signs are (-) and the DENORM is the src
10378 # Handle NANs, infinities, and zeroes as special cases. Divide #
10384 # and return the EXOP if exceptions are enabled. Else, scale the #
10719 # Handle NANs, infinities, and zeroes as special cases. Divide #
10725 # and return the EXOP if exceptions are enabled. Else, scale the #
10742 # DIVIDE: NORMs and DENORMs ONLY!
11057 # Handle NANs, infinities, and zeroes as special cases. Divide #
11058 # norms into extended, single, and double precision. #
11061 # occurred. If so, return default result and maybe EXOP. Else, insert #
11062 # the correct result exponent and return. Set FPSR bits as appropriate. #
11089 # ADD: norms and denorms
11105 or.l %d1,USER_FPSR(%a6) # save exc and ccode bits
11292 # 0x8000000000000000 and this mantissa is the result of rounding non-zero
11296 # so, we do this be re-executing the add using RZ as the rounding mode and
11398 # and return the appropriately signed zero.
11425 # one operand is a ZERO and the other is a DENORM or NORM. scale
11426 # the DENORM or NORM and jump to the regular fadd routine.
11462 # operands are INF and one of {ZERO, INF, DENORM, NORM}
11472 # operands are INF and one of {ZERO, INF, DENORM, NORM}
11510 # Handle NANs, infinities, and zeroes as special cases. Divide #
11511 # norms into extended, single, and double precision. #
11514 # occurred. If so, return default result and maybe EXOP. Else, insert #
11515 # the correct result exponent and return. Set FPSR bits as appropriate. #
11542 # SUB: norms and denorms
11558 or.l %d1,USER_FPSR(%a6) # save exc and ccode bits
11745 # 0x8000000000000000 and this mantissa is the result of rounding non-zero
11749 # so, we do this be re-executing the add using RZ as the rounding mode and
11877 # one operand is a ZERO and the other is a DENORM or a NORM.
11878 # scale the DENORM or NORM and jump to the regular fsub routine.
11953 # Handle NANs, infinities, and zeroes as special cases. Divide #
11959 # and return the EXOP if exceptions are enabled. Else, scale the #
11983 # SQUARE ROOT: norms and denorms ONLY!
12087 # we're on the line here and the distinguising characteristic is whether
12184 # now, round to extended(and don't alter the FPSR).
12889 # get_packed(): fetch a packed operand from memory and then #
12917 # the base reg must be updated for both -(An) and (An)+.
12965 # and NaN operands are dispatched without entering this routine) #
12968 # A1. Convert the bcd exponent to binary by successive adds and #
12971 # digits, rather than 1 integer and 16 fraction digits. #
12975 # adds and muls in FP0. Set the sign according to SM. #
12983 # exponent equal to the exponent from A1 and the zero count #
12984 # added if SM = 1 and subtracted if SM = 0. Scale the #
12997 # tables rounded to RN, RM, and RP, according to the table #
13003 # exponent sign is positive, and dividing FP0 by FP1 if #
13006 # Clean up and return. Check if the final mul or div was inexact. #
13012 # PTENRN, PTENRM, and PTENRP are arrays of powers of 10 rounded
13013 # to nearest, minus, and plus, respectively. The tables include
13043 # 2. Calculate absolute value of exponent in d1 by mul and add.
13068 bfextu %d4{%d3:&4},%d0 # get the digit and zero extend into d0
13078 neg.l %d1 # now negative, make pos and set SE
13080 or.l &0x40000000,(%a0) # and in working bcd
13086 # 1. Calculate absolute value of mantissa in fp0 by mul and add.
13097 # ( ) d4: words 2 and 3 of bcd
13125 bfextu %d4{%d3:&4},%d0 # get the digit and zero extend
13130 # then inc d1 (=2) to point to the next long word and reset d3 to 0
13131 # to initialize the digit offset, and set d2 to 7 for the digit count;
13141 # Check the sign of the mant and make the value in fp0 the same sign.
13153 # if the exp was positive, and added if it was negative. The purpose
13154 # of this is to reduce the value of the exponent and the possibility
13159 # 2. Check M16 and the digits in lwords 2 and 3 in descending order.
13163 # and set SE.
13166 # 2. Check the digits in lwords 3 and 2 in descending order.
13194 # and do append (+) or strip (-) zeros accordingly.
13211 addq.l &8,%d1 # and inc count by 8
13230 or.l &0x40000000,%d4 # and set SE in d4
13231 or.l &0x40000000,(%a0) # and in memory
13276 neg.l %d1 # take abs of exp and clr SE
13278 and.l &0xbfffffff,%d4 # and clr SE in d4
13279 and.l &0xbfffffff,(%a0) # and in memory
13300 # Calculate power-of-ten factor from adjusted and shifted exponent.
13351 clr.l %d3 # clear d3 to force no exc and extended
13369 or.l &0x40000000,(%a0) # and set SE bit
13383 # Check the sign of the adjusted exp and make the value in fp0 the
13403 # Clean up and return with result in fp0.
13410 bclr &inex2_bit+8,%d0 # test for inex2 and clear it
13435 # A1. Set RM and size ext; Set SIGMA = sign of input. #
13471 # function of the original rounding mode and the signs #
13472 # of ISCALE and X. A table is given in the code. #
13500 # or less than LEN -1 digits, adjust ILOG and repeat from #
13502 # result is exactly 10^LEN, decrement ILOG and divide #
13508 # to be a fraction; i.e. (mantissa)/10^LEN and adjusted #
13514 # As in A14 above, the exp is converted to bcd and the #
13575 # A1. Set RM and size ext. Set SIGMA = sign input;
13580 # the input and test for denormalized result.
13582 fmov.l &rm_mode*0x10,%fpcr # set RM and ext
13595 and.w &0x7fff,%d0 # strip sign of normalized exp
13611 and.w &0x7fff,%d0 # strip sign of normalized exp
13622 and.l &0x7fffffff,FP_SCR1(%a6) # create abs(X)
13786 bgt.b k_pos # if pos and > 0, skip this
13805 neg.l %d0 # and take abs of ISCALE
13862 # with a multiply by 10^8 and 10^16, which is exact since
13864 # create a busy stack frame with the mul command and the
13865 # two operands, and allow the fpu to complete the multiply.
13902 # so, we do the multiplication of the exponents and mantissas separately.
13904 # multiplication and guarantee a result without exception.
13985 # mode and precision. The original FPCR is saved in L_SCR1.
13989 and.l &0x00000030,USER_FPCR(%a6) # set size to ext,
14008 # a6: temp pointer to FP_SCR1(a6) - orig value saved and restored
14055 # or less than LEN -1 digits, adjust ILOG and repeat from
14057 # result is exactly 10^LEN, decrement ILOG and divide
14104 # 10^LEN-1 is computed for this test and A14. If the input was
14112 # Compare abs(YINT) to 10^(LEN-1) and 10^LEN
14122 bra.w A6_str # return to A6 and recompute YINT
14127 fbgt.w fix_ex # if greater, fix and redo
14129 addq.l &1,%d6 # and inc ILOG
14130 bra.b A14_st # and continue elsewhere
14135 bra.w A6_str # return to A6 and recompute YINT
14138 # and shouldn't have another; this is to check if abs(YINT) = 10^LEN
14158 addq.l &1,%d6 # and inc ILOG by 1
14159 addq.l &1,%d4 # and inc LEN
14165 # to be a fraction; i.e. (mantissa)/10^LEN and adjusted
14222 and.l &0xffffff80,%d3 # strip off lsb not used by 882
14230 # As in A14 above, the exp is converted to bcd and the
14307 and.l &0xffffff80,%d3 # strip off lsb not used by 882
14347 and.b &0x0f,FP_SCR0(%a6) # clear first nibble of FP_SCR0
14356 bfins %d0,FP_SCR0(%a6){&0:&2} # insert SM and SE into FP_SCR0
14358 # Clean up and restore all registers used.
14429 # shift and a mul by 8 shift. The bits shifted out of the #
14433 # A1. Init d7 to 1. D7 is the byte digit counter, and if 1, the #
14441 # extracts and shifts. The three msbs from d2 will go into d1. #
14446 # A5. Add using the carry the 64-bit quantities in d2:d3 and d4:d5 #
14454 # A7. Decrement d6 (LEN counter) and repeat the loop until zero. #
14513 # A6. Test d7 and branch.
14536 # Clean up and return with result in fp0.
14570 # -(an)+ register gets returned to its pre-exception value and then #
14727 # instruction (data moved in) and the exception was in supervisor