Lines Matching refs:set
42 set _off_chk, 0x00
43 set _off_divbyzero, 0x04
44 set _off_trace, 0x08
45 set _off_access, 0x0c
46 set _off_done, 0x10
48 set _off_cas, 0x14
49 set _off_cas2, 0x18
50 set _off_lock, 0x1c
51 set _off_unlock, 0x20
53 set _off_imr, 0x40
54 set _off_dmr, 0x44
55 set _off_dmw, 0x48
56 set _off_irw, 0x4c
57 set _off_irl, 0x50
58 set _off_drb, 0x54
59 set _off_drw, 0x58
60 set _off_drl, 0x5c
61 set _off_dwb, 0x60
62 set _off_dww, 0x64
63 set _off_dwl, 0x68
261 # This file contains a set of define statements for constants
265 set LOCAL_SIZE, 96 # stack frame size(bytes)
266 set LV, -LOCAL_SIZE # stack offset
268 set EXC_ISR, 0x4 # stack status register
269 set EXC_IPC, 0x6 # stack pc
270 set EXC_IVOFF, 0xa # stacked vector offset
272 set EXC_AREGS, LV+64 # offset of all address regs
273 set EXC_DREGS, LV+32 # offset of all data regs
275 set EXC_A7, EXC_AREGS+(7*4) # offset of a7
276 set EXC_A6, EXC_AREGS+(6*4) # offset of a6
277 set EXC_A5, EXC_AREGS+(5*4) # offset of a5
278 set EXC_A4, EXC_AREGS+(4*4) # offset of a4
279 set EXC_A3, EXC_AREGS+(3*4) # offset of a3
280 set EXC_A2, EXC_AREGS+(2*4) # offset of a2
281 set EXC_A1, EXC_AREGS+(1*4) # offset of a1
282 set EXC_A0, EXC_AREGS+(0*4) # offset of a0
283 set EXC_D7, EXC_DREGS+(7*4) # offset of d7
284 set EXC_D6, EXC_DREGS+(6*4) # offset of d6
285 set EXC_D5, EXC_DREGS+(5*4) # offset of d5
286 set EXC_D4, EXC_DREGS+(4*4) # offset of d4
287 set EXC_D3, EXC_DREGS+(3*4) # offset of d3
288 set EXC_D2, EXC_DREGS+(2*4) # offset of d2
289 set EXC_D1, EXC_DREGS+(1*4) # offset of d1
290 set EXC_D0, EXC_DREGS+(0*4) # offset of d0
292 set EXC_TEMP, LV+16 # offset of temp stack space
294 set EXC_SAVVAL, LV+12 # offset of old areg value
295 set EXC_SAVREG, LV+11 # offset of old areg index
297 set SPCOND_FLG, LV+10 # offset of spc condition flg
299 set EXC_CC, LV+8 # offset of cc register
300 set EXC_EXTWPTR, LV+4 # offset of current PC
301 set EXC_EXTWORD, LV+2 # offset of current ext opword
302 set EXC_OPWORD, LV+0 # offset of current opword
307 set mia7_flg, 0x04 # (a7)+ flag
308 set mda7_flg, 0x08 # -(a7) flag
309 set ichk_flg, 0x10 # chk exception flag
310 set idbyz_flg, 0x20 # divbyzero flag
311 set restore_flg, 0x40 # restore -(an)+ flag
312 set immed_flg, 0x80 # immediate data flag
314 set mia7_bit, 0x2 # (a7)+ bit
315 set mda7_bit, 0x3 # -(a7) bit
316 set ichk_bit, 0x4 # chk exception bit
317 set idbyz_bit, 0x5 # divbyzero bit
318 set restore_bit, 0x6 # restore -(a7)+ bit
319 set immed_bit, 0x7 # immediate data bit
324 set BYTE, 1 # len(byte) == 1 byte
325 set WORD, 2 # len(word) == 2 bytes
326 set LONG, 4 # len(longword) == 4 bytes
841 bset &0x2,0xd(%sp) # set supervisor TM bit
889 # future access error; if -(a7), set mda7_flg in #
893 # future access error; if (a7)+, set mia7_flg in #
900 # #<data> - return address of immediate value; set immed_flg #
1047 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag
1058 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag
1069 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag
1080 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag
1091 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag
1102 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag
1113 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag
1117 mov.b &mia7_flg,SPCOND_FLG(%a6) # set "special case" flag
1136 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag
1147 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag
1158 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag
1169 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag
1180 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag
1191 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag
1202 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag
1206 mov.b &mda7_flg,SPCOND_FLG(%a6) # set "special case" flag
1377 mov.b &immed_flg,SPCOND_FLG(%a6) # set immediate flag
1883 # If the instruction is chk2 and the Rn value is out-of-bounds, set #
1976 # To set the ccodes correctly:
2005 # if the 'N' bit was set by the operation.
2007 btst &0x0, %d4 # is 'N' bit set?
2011 mov.b &ichk_flg,SPCOND_FLG(%a6) # set "special case" flag
2074 set NDIVISOR, EXC_TEMP+0x0
2075 set NDIVIDEND, EXC_TEMP+0x1
2076 set NDRSAVE, EXC_TEMP+0x2
2077 set NDQSAVE, EXC_TEMP+0x4
2078 set DDSECOND, EXC_TEMP+0x6
2079 set DDQUOTIENT, EXC_TEMP+0x8
2080 set DDNORMAL, EXC_TEMP+0xc
2191 # at this point, result is normal so ccodes are set based on result.
2193 tst.l %d6 # set %ccode bits
2207 bset &0x1, EXC_CC+1(%a6) # 'V' set on overflow
2214 ori.b &idbyz_flg,SPCOND_FLG(%a6) # set "special case" flag
2227 # signed/unsigned flag ddusign must be set (0=unsigned,1=signed). #
2229 # v (overflow) bit is set in the saved %ccr. If overflow, the dividend #
2327 tst.w %d0 # is upper word set?
2387 subq.l &0x1, %d7 # set for loop count
2636 # now, grab the condition codes. only one that can be set is 'N'.
2637 # 'N' CAN be set if the operation is unsigned if bit 63 is set.
2638 mov.w %cc, %d7 # fetch %ccr to see if 'N' set
2651 # save the zero result to the register file and set the 'Z' ccode bit.
2656 movq.l &0x4, %d7 # set 'Z' ccode bit
2657 bra.b mul64_ccode_set # finish ccode set
2758 set ADDR1, EXC_TEMP+0xc
2759 set ADDR2, EXC_TEMP+0x0
2760 set DC2, EXC_TEMP+0xa
2761 set DC1, EXC_TEMP+0x8
2955 # initial register set before emulation exception #
2976 # set the condition codes. Finally, these routines will call #
3000 set DC, EXC_TEMP+0x8
3001 set ADDR, EXC_TEMP+0x4
3019 st %d7 # set d7 for longword size
3034 sne %d6 # set on supervisor mode
3106 sne %d7 # set d7 accordingly
3194 # (3) Save current SFC/DFC (ASSUMED TO BE EQUAL!!!); Then set #
3306 # shares the same set, then the "plpaw" for ADDR2 can push the ADDR1
3307 # entries from the ATC. so, we do a second set of "plpa"s.
3608 # shares the same set, then the "plpaw" for ADDR2 can push the ADDR1
3609 # entries from the ATC. so, we do a second set of "plpa"s.
3814 # (3) Save current DFC/SFC (ASSUMED TO BE EQUAL!!!); Then set #