Lines Matching defs:and
9 THE SOFTWARE is provided on an "AS IS" basis and without warranty.
13 and any warranty against infringement with regard to the SOFTWARE
14 (INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
21 Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
23 You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
24 so long as this entire notice is retained without alteration in any modified and/or
25 redistributed versions, and that such modified versions are clearly identified as such.
31 # and contains the entry points into the package. The user, in
39 # it makes the ISP code easier to read and more mainatinable.
343 # _chk2_cmp2() - emulate "cmp2" and "chk2" #
367 # memory and decodes it to determine which of the unimplemented #
373 # and "chk2" can cause a "Chk" exception. In both cases, the current #
375 # of the correct exception type and an exit must be made through #
378 # a Trace exception stack frame must be created and an exit made #
382 # access error frame must be created and an exit made through #
388 # address and data registers to the stack. Although this may seem to #
390 # access these register files for things like data retrieval and <ea> #
423 # fetch the opword and first extension word pointed to by the stacked pc
424 # and store them to the stack for now
478 # mul64() may use ()+ addressing and may, therefore, alter a7
491 # div64() may use ()+ addressing and may, therefore, alter a7.
542 # the cases of "cas Dc,Du,(a7)+" and "cas Dc,Du,-(a7)" used from supervisor
543 # mode are simply not considered valid and therefore are not handled.
573 # info and prepare for rte
603 # format number zero and jump to the user supplied hook "_real_trace()".
650 # and jump to the user supplied entry point "_real_chk()".
683 # instruction exception frame and jump to the user supplied entry point
717 # instruction exception frame and jump to the user supplied entry point
756 # format number zero and jump to the user supplied hook "_real_trace()".
883 # uses byte-sized operands, only handle word and long operations. #
916 # MODE and REG are taken from the EXC_OPWORD.
1605 # and the failing address to the routine that creates the new frame.
1636 # Decode the movep instruction words stored at EXC_OPWORD and #
1639 # returns a failing value, we must pass the failing address and a FSLW #
1655 and.w &0x7,%d0 # extract Ay from opcode word
1668 and.w &0x7,%d0 # extract Dx from opcode word
1744 # determines the dest register, and then writes the bytes into it.
1795 and.w &0x7,%d1 # extract Dx from opcode word
1825 and.w &0x7,%d1 # extract Dx from opcode word
1833 # and the failing address to the routine that creates the new frame.
1882 # The comparisons are made and the condition codes calculated. #
1883 # If the instruction is chk2 and the Rn value is out-of-bounds, set #
1886 # address and FSLW to the isp_dacc() routine. #
1899 and.w &0xf, %d0 # extract reg bits
1908 # bound into d0 and the higher bound into d1.
1978 # (2) save 'Z' and 'N' bits from ((hi - lo) - (Rn - hi))
1979 # (3) keep 'X', 'N', and 'V' from before instruction
1991 andi.b &0x5, %d3 # keep 'Z' and 'N'
2003 # this code handles the only difference between chk2 and cmp2. chk2 would
2016 # and the failing address to the routine that creates the new frame.
2064 # If the operands are signed, make them unsigned and save the #
2070 # quotient and remainder in the appropriate data registers on the stack.#
2101 and.w &0x7, %d0
2103 and.w &0x7, %d1
2107 # fetch %dr and %dq directly off stack since all regs are saved there
2111 # separate signed and unsigned divide
2163 # separate into signed and unsigned finishes.
2221 # For this implementation b=2**16, and the target is U1U2U3U4/V1V2, #
2222 # where U,V are words of the quadword dividend and longword divisor, #
2223 # and U1, V1 are the most significant words. #
2226 # in %d6. The divisor must be in the variable ddivisor, and the #
2239 # Since the divisor is only a word (and larger than the mslw of the dividend),
2245 # longword of the dividend as (0) remainder (see Knuth) and merely complete
2246 # the last two divisions to get a quotient longword and word remainder:
2265 mov.l %d1, %d6 # and quotient
2272 # digit (word). After subtraction, the dividend is shifted and the
2273 # process repeated. Before beginning, the divisor and quotient are
2308 # now test the trial quotient and adjust. This step plus the
2334 subq.l &0x1, %d1 # yes, decrement and recheck
2337 # now test the word by multiplying it by the divisor (V1V2) and comparing
2368 # first quotient digit now correct. store digit and shift the
2398 # factors for the 32X32->64 multiplication are in %d5 and %d6.
2412 # now use swap and addx to consolidate to two longwords
2462 # and the failing address to the routine that creates the new frame.
2502 # If the operands are signed, make them unsigned and save the #
2504 # unsigned multiplies and "add" instructions. Store the high and low #
2520 # must extract the register number and fetch the operand from the stack.
2525 # multiplier is in %d3. now, extract Dl and Dh fields and fetch the
2542 # multiplier is in %d3 and multiplicand is in %d4.
2544 # to unsigned and the result sign is saved for the end.
2606 # now, clear lo, put hi in lo reg, and add to [4]
2620 # -negate all bits and add 1
2645 or.b %d7, %d6 # group 'X' and 'N'
2651 # save the zero result to the register file and set the 'Z' ccode bit.
2662 # must calculate the <ea> and go fetch the 32-bit operand.
2697 # and the failing address to the routine that creates the new frame.
2741 # Decode the instruction and fetch the appropriate Update and #
2921 # (external and internal to package) #
2925 # (external and internal to package) #
2963 # instruction word and fetch the "compare" (DC) and "update" (Du) #
2986 # an emulation operand access failed and the operating system would #
3161 # This is the start of the cas and cas2 "core" emulation code. #
3215 # the bus (and assert LOCKE*) using BUSCR and the final move. #
3222 # depending on the size of the operation and the misalignment of the #
3283 # load the SFC and DFC with the appropriate mode.
3304 # if ADDR1 was ATC resident before the above "plpaw" and was executed
3305 # and it was the next entry scheduled for replacement and ADDR2
3585 # load the SFC and DFC with the appropriate mode.
3606 # if ADDR1 was ATC resident before the above "plpaw" and was executed
3607 # and it was the next entry scheduled for replacement and ADDR2
3832 # the bus (and assert LOCKE*) using BUSCR and the final move. #
3839 # depending on the size of the operation and the misalignment of the #
3894 # load the SFC and DFC with the appropriate mode.
4052 # load the SFC and DFC with the appropriate mode.
4198 # load the SFC and DFC with the appropriate mode.