Lines Matching refs:insn
31 union loongarch_instruction *insn = &ctx->image[ctx->idx]; \
32 emit_##func(insn, ##__VA_ARGS__); \
75 static inline void emit_ldbu(union loongarch_instruction *insn,
78 insn->reg2i12_format.opcode = ldbu_op;
79 insn->reg2i12_format.simmediate = imm;
80 insn->reg2i12_format.rd = rd;
81 insn->reg2i12_format.rj = rj;
84 static inline void emit_ldhu(union loongarch_instruction *insn,
87 insn->reg2i12_format.opcode = ldhu_op;
88 insn->reg2i12_format.simmediate = imm;
89 insn->reg2i12_format.rd = rd;
90 insn->reg2i12_format.rj = rj;
93 static inline void emit_ldwu(union loongarch_instruction *insn,
96 insn->reg2i12_format.opcode = ldwu_op;
97 insn->reg2i12_format.simmediate = imm;
98 insn->reg2i12_format.rd = rd;
99 insn->reg2i12_format.rj = rj;
102 static inline void emit_ldd(union loongarch_instruction *insn,
105 insn->reg2i12_format.opcode = ldd_op;
106 insn->reg2i12_format.simmediate = imm;
107 insn->reg2i12_format.rd = rd;
108 insn->reg2i12_format.rj = rj;
111 static inline void emit_stb(union loongarch_instruction *insn,
114 insn->reg2i12_format.opcode = stb_op;
115 insn->reg2i12_format.simmediate = imm;
116 insn->reg2i12_format.rd = rd;
117 insn->reg2i12_format.rj = rj;
120 static inline void emit_sth(union loongarch_instruction *insn,
123 insn->reg2i12_format.opcode = sth_op;
124 insn->reg2i12_format.simmediate = imm;
125 insn->reg2i12_format.rd = rd;
126 insn->reg2i12_format.rj = rj;
129 static inline void emit_stw(union loongarch_instruction *insn,
132 insn->reg2i12_format.opcode = stw_op;
133 insn->reg2i12_format.simmediate = imm;
134 insn->reg2i12_format.rd = rd;
135 insn->reg2i12_format.rj = rj;
138 static inline void emit_std(union loongarch_instruction *insn,
141 insn->reg2i12_format.opcode = std_op;
142 insn->reg2i12_format.simmediate = imm;
143 insn->reg2i12_format.rd = rd;
144 insn->reg2i12_format.rj = rj;
147 static inline void emit_ldxbu(union loongarch_instruction *insn, enum loongarch_gpr rd,
150 insn->reg3_format.opcode = ldxbu_op;
151 insn->reg3_format.rd = rd;
152 insn->reg3_format.rj = rj;
153 insn->reg3_format.rk = rk;
156 static inline void emit_ldxhu(union loongarch_instruction *insn, enum loongarch_gpr rd,
159 insn->reg3_format.opcode = ldxhu_op;
160 insn->reg3_format.rd = rd;
161 insn->reg3_format.rj = rj;
162 insn->reg3_format.rk = rk;
165 static inline void emit_ldxwu(union loongarch_instruction *insn, enum loongarch_gpr rd,
168 insn->reg3_format.opcode = ldxwu_op;
169 insn->reg3_format.rd = rd;
170 insn->reg3_format.rj = rj;
171 insn->reg3_format.rk = rk;
174 static inline void emit_ldxd(union loongarch_instruction *insn, enum loongarch_gpr rd,
177 insn->reg3_format.opcode = ldxd_op;
178 insn->reg3_format.rd = rd;
179 insn->reg3_format.rj = rj;
180 insn->reg3_format.rk = rk;
183 static inline void emit_stxb(union loongarch_instruction *insn, enum loongarch_gpr rd,
186 insn->reg3_format.opcode = stxb_op;
187 insn->reg3_format.rd = rd;
188 insn->reg3_format.rj = rj;
189 insn->reg3_format.rk = rk;
192 static inline void emit_stxh(union loongarch_instruction *insn, enum loongarch_gpr rd,
195 insn->reg3_format.opcode = stxh_op;
196 insn->reg3_format.rd = rd;
197 insn->reg3_format.rj = rj;
198 insn->reg3_format.rk = rk;
201 static inline void emit_stxw(union loongarch_instruction *insn, enum loongarch_gpr rd,
204 insn->reg3_format.opcode = stxw_op;
205 insn->reg3_format.rd = rd;
206 insn->reg3_format.rj = rj;
207 insn->reg3_format.rk = rk;
210 static inline void emit_stxd(union loongarch_instruction *insn, enum loongarch_gpr rd,
213 insn->reg3_format.opcode = stxd_op;
214 insn->reg3_format.rd = rd;
215 insn->reg3_format.rj = rj;
216 insn->reg3_format.rk = rk;
219 static inline void emit_amaddw(union loongarch_instruction *insn, enum loongarch_gpr rd,
222 insn->reg3_format.opcode = amaddw_op;
223 insn->reg3_format.rd = rd;
224 insn->reg3_format.rk = rk;
225 insn->reg3_format.rj = rj;
228 static inline void emit_amaddd(union loongarch_instruction *insn, enum loongarch_gpr rd,
231 insn->reg3_format.opcode = amaddd_op;
232 insn->reg3_format.rd = rd;
233 insn->reg3_format.rk = rk;
234 insn->reg3_format.rj = rj;
237 static inline void emit_addd(union loongarch_instruction *insn, enum loongarch_gpr rd,
240 insn->reg3_format.opcode = addd_op;
241 insn->reg3_format.rd = rd;
242 insn->reg3_format.rj = rj;
243 insn->reg3_format.rk = rk;
246 static inline void emit_addiw(union loongarch_instruction *insn,
249 insn->reg2i12_format.opcode = addiw_op;
250 insn->reg2i12_format.simmediate = imm;
251 insn->reg2i12_format.rd = rd;
252 insn->reg2i12_format.rj = rj;
255 static inline void emit_addid(union loongarch_instruction *insn,
258 insn->reg2i12_format.opcode = addid_op;
259 insn->reg2i12_format.simmediate = imm;
260 insn->reg2i12_format.rd = rd;
261 insn->reg2i12_format.rj = rj;
264 static inline void emit_subd(union loongarch_instruction *insn, enum loongarch_gpr rd,
267 insn->reg3_format.opcode = subd_op;
268 insn->reg3_format.rd = rd;
269 insn->reg3_format.rj = rj;
270 insn->reg3_format.rk = rk;
273 static inline void emit_muld(union loongarch_instruction *insn, enum loongarch_gpr rd,
276 insn->reg3_format.opcode = muld_op;
277 insn->reg3_format.rd = rd;
278 insn->reg3_format.rj = rj;
279 insn->reg3_format.rk = rk;
282 static inline void emit_divdu(union loongarch_instruction *insn, enum loongarch_gpr rd,
285 insn->reg3_format.opcode = divdu_op;
286 insn->reg3_format.rd = rd;
287 insn->reg3_format.rj = rj;
288 insn->reg3_format.rk = rk;
291 static inline void emit_moddu(union loongarch_instruction *insn, enum loongarch_gpr rd,
294 insn->reg3_format.opcode = moddu_op;
295 insn->reg3_format.rd = rd;
296 insn->reg3_format.rj = rj;
297 insn->reg3_format.rk = rk;
300 static inline void emit_and(union loongarch_instruction *insn, enum loongarch_gpr rd,
303 insn->reg3_format.opcode = and_op;
304 insn->reg3_format.rd = rd;
305 insn->reg3_format.rj = rj;
306 insn->reg3_format.rk = rk;
309 static inline void emit_andi(union loongarch_instruction *insn,
312 insn->reg2ui12_format.opcode = andi_op;
313 insn->reg2ui12_format.simmediate = imm;
314 insn->reg2ui12_format.rd = rd;
315 insn->reg2ui12_format.rj = rj;
318 static inline void emit_or(union loongarch_instruction *insn, enum loongarch_gpr rd,
321 insn->reg3_format.opcode = or_op;
322 insn->reg3_format.rd = rd;
323 insn->reg3_format.rj = rj;
324 insn->reg3_format.rk = rk;
327 static inline void emit_ori(union loongarch_instruction *insn,
330 insn->reg2ui12_format.opcode = ori_op;
331 insn->reg2ui12_format.simmediate = imm;
332 insn->reg2ui12_format.rd = rd;
333 insn->reg2ui12_format.rj = rj;
336 static inline void emit_xor(union loongarch_instruction *insn, enum loongarch_gpr rd,
339 insn->reg3_format.opcode = xor_op;
340 insn->reg3_format.rd = rd;
341 insn->reg3_format.rj = rj;
342 insn->reg3_format.rk = rk;
345 static inline void emit_xori(union loongarch_instruction *insn,
348 insn->reg2ui12_format.opcode = xori_op;
349 insn->reg2ui12_format.simmediate = imm;
350 insn->reg2ui12_format.rd = rd;
351 insn->reg2ui12_format.rj = rj;
354 static inline void emit_lu12iw(union loongarch_instruction *insn,
357 insn->reg1i20_format.opcode = lu12iw_op;
358 insn->reg1i20_format.simmediate = imm;
359 insn->reg1i20_format.rd = rd;
362 static inline void emit_lu32id(union loongarch_instruction *insn,
365 insn->reg1i20_format.opcode = lu32id_op;
366 insn->reg1i20_format.simmediate = imm;
367 insn->reg1i20_format.rd = rd;
370 static inline void emit_lu52id(union loongarch_instruction *insn,
373 insn->reg2i12_format.opcode = lu52id_op;
374 insn->reg2i12_format.simmediate = imm;
375 insn->reg2i12_format.rd = rd;
376 insn->reg2i12_format.rj = rj;
379 static inline void emit_sllw(union loongarch_instruction *insn, enum loongarch_gpr rd,
382 insn->reg3_format.opcode = sllw_op;
383 insn->reg3_format.rd = rd;
384 insn->reg3_format.rj = rj;
385 insn->reg3_format.rk = rk;
388 static inline void emit_slliw(union loongarch_instruction *insn,
391 insn->reg2ui5_format.opcode = slliw_op;
392 insn->reg2ui5_format.simmediate = imm;
393 insn->reg2ui5_format.rd = rd;
394 insn->reg2ui5_format.rj = rj;
397 static inline void emit_slld(union loongarch_instruction *insn, enum loongarch_gpr rd,
400 insn->reg3_format.opcode = slld_op;
401 insn->reg3_format.rd = rd;
402 insn->reg3_format.rj = rj;
403 insn->reg3_format.rk = rk;
406 static inline void emit_sllid(union loongarch_instruction *insn,
409 insn->reg2ui6_format.opcode = sllid_op;
410 insn->reg2ui6_format.simmediate = imm;
411 insn->reg2ui6_format.rd = rd;
412 insn->reg2ui6_format.rj = rj;
415 static inline void emit_srlw(union loongarch_instruction *insn, enum loongarch_gpr rd,
418 insn->reg3_format.opcode = srlw_op;
419 insn->reg3_format.rd = rd;
420 insn->reg3_format.rj = rj;
421 insn->reg3_format.rk = rk;
424 static inline void emit_srliw(union loongarch_instruction *insn,
427 insn->reg2ui5_format.opcode = srliw_op;
428 insn->reg2ui5_format.simmediate = imm;
429 insn->reg2ui5_format.rd = rd;
430 insn->reg2ui5_format.rj = rj;
433 static inline void emit_srld(union loongarch_instruction *insn, enum loongarch_gpr rd,
436 insn->reg3_format.opcode = srld_op;
437 insn->reg3_format.rd = rd;
438 insn->reg3_format.rj = rj;
439 insn->reg3_format.rk = rk;
442 static inline void emit_srlid(union loongarch_instruction *insn,
445 insn->reg2ui6_format.opcode = srlid_op;
446 insn->reg2ui6_format.simmediate = imm;
447 insn->reg2ui6_format.rd = rd;
448 insn->reg2ui6_format.rj = rj;
451 static inline void emit_sraw(union loongarch_instruction *insn, enum loongarch_gpr rd,
454 insn->reg3_format.opcode = sraw_op;
455 insn->reg3_format.rd = rd;
456 insn->reg3_format.rj = rj;
457 insn->reg3_format.rk = rk;
460 static inline void emit_sraiw(union loongarch_instruction *insn,
463 insn->reg2ui5_format.opcode = sraid_op;
464 insn->reg2ui5_format.simmediate = imm;
465 insn->reg2ui5_format.rd = rd;
466 insn->reg2ui5_format.rj = rj;
469 static inline void emit_srad(union loongarch_instruction *insn, enum loongarch_gpr rd,
472 insn->reg3_format.opcode = srad_op;
473 insn->reg3_format.rd = rd;
474 insn->reg3_format.rj = rj;
475 insn->reg3_format.rk = rk;
478 static inline void emit_sraid(union loongarch_instruction *insn,
481 insn->reg2ui6_format.opcode = sraid_op;
482 insn->reg2ui6_format.simmediate = imm;
483 insn->reg2ui6_format.rd = rd;
484 insn->reg2ui6_format.rj = rj;
487 static inline void emit_beq(union loongarch_instruction *insn,
490 insn->reg2i16_format.opcode = beq_op;
491 insn->reg2i16_format.simmediate = offset;
492 insn->reg2i16_format.rj = rj;
493 insn->reg2i16_format.rd = rd;
496 static inline void emit_bne(union loongarch_instruction *insn,
499 insn->reg2i16_format.opcode = bne_op;
500 insn->reg2i16_format.simmediate = offset;
501 insn->reg2i16_format.rj = rj;
502 insn->reg2i16_format.rd = rd;
505 static inline void emit_blt(union loongarch_instruction *insn,
508 insn->reg2i16_format.opcode = blt_op;
509 insn->reg2i16_format.simmediate = offset;
510 insn->reg2i16_format.rj = rj;
511 insn->reg2i16_format.rd = rd;
514 static inline void emit_bge(union loongarch_instruction *insn,
517 insn->reg2i16_format.opcode = bge_op;
518 insn->reg2i16_format.simmediate = offset;
519 insn->reg2i16_format.rj = rj;
520 insn->reg2i16_format.rd = rd;
523 static inline void emit_bltu(union loongarch_instruction *insn,
526 insn->reg2i16_format.opcode = bltu_op;
527 insn->reg2i16_format.simmediate = offset;
528 insn->reg2i16_format.rj = rj;
529 insn->reg2i16_format.rd = rd;
532 static inline void emit_bgeu(union loongarch_instruction *insn,
535 insn->reg2i16_format.opcode = bgeu_op;
536 insn->reg2i16_format.simmediate = offset;
537 insn->reg2i16_format.rj = rj;
538 insn->reg2i16_format.rd = rd;
541 static inline void emit_b(union loongarch_instruction *insn, int offset)
549 insn->reg0i26_format.opcode = b_op;
550 insn->reg0i26_format.simmediate_l = simmediate_l;
551 insn->reg0i26_format.simmediate_h = simmediate_h;
554 static inline void emit_jirl(union loongarch_instruction *insn,
557 insn->reg2i16_format.opcode = jirl_op;
558 insn->reg2i16_format.simmediate = offset;
559 insn->reg2i16_format.rd = rd;
560 insn->reg2i16_format.rj = rj;
563 static inline void emit_pcaddu18i(union loongarch_instruction *insn,
566 insn->reg1i20_format.opcode = pcaddu18i_op;
567 insn->reg1i20_format.simmediate = imm;
568 insn->reg1i20_format.rd = rd;
571 static inline void emit_revb2h(union loongarch_instruction *insn,
574 insn->reg2_format.opcode = revb2h_op;
575 insn->reg2_format.rd = rd;
576 insn->reg2_format.rj = rj;
579 static inline void emit_revb2w(union loongarch_instruction *insn,
582 insn->reg2_format.opcode = revb2w_op;
583 insn->reg2_format.rd = rd;
584 insn->reg2_format.rj = rj;
587 static inline void emit_revbd(union loongarch_instruction *insn,
590 insn->reg2_format.opcode = revbd_op;
591 insn->reg2_format.rd = rd;
592 insn->reg2_format.rj = rj;