Lines Matching refs:data
64 #define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */
84 #define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
85 #define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
230 u32 data_bits : 8, /* # data bits covered by
259 #define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is
262 #define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is
311 start : 8, /* 47-40 lsb of data to
351 u64 pcli_data; /* 64-bit data, tag, protection bits .. */
352 u64 pcli_data_len; /* data length in bits */
495 dl : 1, /* Failure in data part
545 dtr : 1, /* Fail in data TR */
547 dtc : 1, /* Fail in data TC */
945 * Flush the processor instruction or data caches. *PROGRESS must be
969 /* Initialize the tags and data of a data or unified cache line of
982 /* Read the data and tag of a processor controlled cache line for diags */
1005 /* Write the data and tag of a processor-controlled cache line for diags */
1007 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
1011 physical_addr, data);
1041 /* Return the number of instruction and data debug register pairs */
1731 /* data structure for getting information on logical to physical mappings */