Lines Matching defs:timer
32 static struct timer_regs __iomem *timer;
66 ((soc_readl(&timer->emumgt) & (0xf << 16)) >> 16)
79 u32 tcr = soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK;
81 soc_writel(tcr, &timer->tcr);
82 soc_writel(period - 1, &timer->prdlo);
83 soc_writel(0, &timer->cntlo);
85 soc_writel(tcr, &timer->tcr);
95 /* disable timer, reset count */
96 soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
97 soc_writel(0, &timer->prdlo);
100 val = soc_readl(&timer->tcr);
101 soc_writel(val & ~(TCR_CLKSRCLO | TCR_PWIDLO_MASK), &timer->tcr);
104 val = soc_readl(&timer->tgcr) & ~TGCR_TIMMODE_MASK;
105 soc_writel(val, &timer->tgcr);
106 soc_writel(val | (TGCR_TIMLORS | TGCR_TIMMODE_UD32), &timer->tgcr);
111 /* disable timer, reset count */
112 soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
113 soc_writel(0, &timer->prdlo);
190 pr_debug("Cannot find ti,c64x+timer64 timer.\n");
195 timer = of_iomap(np, 0);
196 if (!timer) {
197 pr_debug("%pOF: Cannot map timer registers.\n", np);
200 pr_debug("%pOF: Timer registers=%p.\n", np, timer);
205 iounmap(timer);
215 * It is necessary to enable the timer block here because
216 * the TIMER_DIVISOR macro needs to read a timer register
234 if (request_irq(cd->irq, timer_interrupt, IRQF_TIMER, "timer",
236 pr_err("Failed to request irq %d (timer)\n", cd->irq);