Lines Matching refs:parent
39 .parent = &clkin1,
45 .parent = &c6x_soc_pll1.sysclks[0],
50 .parent = &c6x_soc_pll1.sysclks[0],
55 .parent = &c6x_soc_pll1.sysclks[0],
60 .parent = &c6x_soc_pll1.sysclks[0],
65 .parent = &c6x_soc_pll1.sysclks[0],
70 .parent = &c6x_soc_pll1.sysclks[0],
75 .parent = &c6x_soc_pll1.sysclks[0],
80 .parent = &c6x_soc_pll1.sysclks[0],
85 .parent = &c6x_soc_pll1.sysclks[0],
90 .parent = &c6x_soc_pll1.sysclks[0],
95 .parent = &c6x_soc_pll1.sysclks[0],
100 .parent = &c6x_soc_pll1.sysclks[0],
105 .parent = &c6x_soc_pll1.sysclks[0],
110 .parent = &c6x_soc_pll1.sysclks[0],
115 .parent = &c6x_soc_pll1.sysclks[0],
120 .parent = &c6x_soc_pll1.sysclks[0],
182 c6x_core_clk.parent = &sysclks[0];
183 c6x_i2c_clk.parent = &sysclks[3];
184 c6x_watchdog_clk.parent = &sysclks[3];
185 c6x_mdio_clk.parent = &sysclks[3];
222 c6x_core_clk.parent = &sysclks[1];
223 c6x_i2c_clk.parent = &sysclks[3];
224 c6x_watchdog_clk.parent = &sysclks[5];
225 c6x_mdio_clk.parent = &sysclks[5];
277 c6x_core_clk.parent = &sysclks[get_coreid() + 1];
278 c6x_i2c_clk.parent = &sysclks[8];
279 c6x_watchdog_clk.parent = &sysclks[8];
280 c6x_mdio_clk.parent = &sysclks[5];
326 c6x_core_clk.parent = &sysclks[7];
327 c6x_i2c_clk.parent = &sysclks[10];
328 c6x_watchdog_clk.parent = &sysclks[10];
329 c6x_mcbsp1_clk.parent = &sysclks[10];
330 c6x_mcbsp2_clk.parent = &sysclks[10];
391 c6x_core_clk.parent = &sysclks[0];
392 c6x_i2c_clk.parent = &sysclks[7];