Lines Matching defs:parent
29 if (clk->parent)
30 __clk_enable(clk->parent);
40 if (clk->parent)
41 __clk_disable(clk->parent);
128 int clk_set_parent(struct clk *clk, struct clk *parent)
135 /* Cannot change parent on enabled clock */
140 clk->parent = parent;
142 list_add(&clk->childnode, &clk->parent->children);
160 if (WARN(clk->parent && !clk->parent->rate,
161 "CLK: %s parent %s has no rate!\n",
162 clk->name, clk->parent->name))
167 if (clk->parent)
168 list_add_tail(&clk->childnode, &clk->parent->children);
179 /* Otherwise, default to parent rate */
180 else if (clk->parent)
181 clk->rate = clk->parent->rate;
211 if (WARN_ON(!clk->parent))
214 rate = clk->parent->rate;
216 /* the parent must be a PLL */
217 if (WARN_ON(!clk->parent->pll_data))
220 pll = clk->parent->pll_data;
256 if (WARN_ON(!clk->parent))
259 pr_debug("%s: (parent %s) rate = %lu KHz\n",
260 clk->name, clk->parent->name, clk->parent->rate / 1000);
262 return clk->parent->rate;
276 rate = pll->input_rate = clk->parent->rate;
312 pll->num, clk->parent->rate / 1000000,
316 pll->num, clk->parent->rate / 1000000);
339 else if (clk->parent)
375 dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
382 if (parent->flags & CLK_PLL)
390 i = strlen(parent->name);
391 memcpy(buf + nest, parent->name,
395 buf, parent->usecount, state, clk_get_rate(parent));
399 list_for_each_entry(clk, &parent->children, childnode) {
413 if (!clk->parent)