Lines Matching refs:imm
175 static bool is_addsub_imm(u32 imm)
178 return !(imm & ~0xfff) || !(imm & ~0xfff000);
436 const s32 imm = insn->imm;
446 #define check_imm(bits, imm) do { \
447 if ((((imm) > 0) && ((imm) >> (bits))) || \
448 (((imm) < 0) && (~(imm) >> (bits)))) { \
449 pr_info("[%2d] imm=%d(0x%x) out of range\n", \
450 i, imm, imm); \
454 #define check_imm19(imm) check_imm(19, imm)
455 #define check_imm26(imm) check_imm(26, imm)
519 /* dst = BSWAP##imm(dst) */
529 switch (imm) {
545 switch (imm) {
559 /* dst = imm */
562 emit_a64_mov_i(is64, dst, imm, ctx);
564 /* dst = dst OP imm */
567 if (is_addsub_imm(imm)) {
568 emit(A64_ADD_I(is64, dst, dst, imm), ctx);
569 } else if (is_addsub_imm(-imm)) {
570 emit(A64_SUB_I(is64, dst, dst, -imm), ctx);
572 emit_a64_mov_i(is64, tmp, imm, ctx);
578 if (is_addsub_imm(imm)) {
579 emit(A64_SUB_I(is64, dst, dst, imm), ctx);
580 } else if (is_addsub_imm(-imm)) {
581 emit(A64_ADD_I(is64, dst, dst, -imm), ctx);
583 emit_a64_mov_i(is64, tmp, imm, ctx);
589 a64_insn = A64_AND_I(is64, dst, dst, imm);
593 emit_a64_mov_i(is64, tmp, imm, ctx);
599 a64_insn = A64_ORR_I(is64, dst, dst, imm);
603 emit_a64_mov_i(is64, tmp, imm, ctx);
609 a64_insn = A64_EOR_I(is64, dst, dst, imm);
613 emit_a64_mov_i(is64, tmp, imm, ctx);
619 emit_a64_mov_i(is64, tmp, imm, ctx);
624 emit_a64_mov_i(is64, tmp, imm, ctx);
629 emit_a64_mov_i(is64, tmp2, imm, ctx);
635 emit(A64_LSL(is64, dst, dst, imm), ctx);
639 emit(A64_LSR(is64, dst, dst, imm), ctx);
643 emit(A64_ASR(is64, dst, dst, imm), ctx);
718 /* IF (dst COND imm) JUMP off */
739 if (is_addsub_imm(imm)) {
740 emit(A64_CMP_I(is64, dst, imm), ctx);
741 } else if (is_addsub_imm(-imm)) {
742 emit(A64_CMN_I(is64, dst, -imm), ctx);
744 emit_a64_mov_i(is64, tmp, imm, ctx);
750 a64_insn = A64_TST_I(is64, dst, imm);
754 emit_a64_mov_i(is64, tmp, imm, ctx);
796 imm64 = (u64)insn1.imm << 32 | (u32)imm;
845 /* ST: *(size *)(dst + off) = imm */
850 /* Load imm to a register then store it */
852 emit_a64_mov_i(1, tmp, imm, ctx);