Lines Matching refs:Rt
23 #define A64_COMP_BRANCH(sf, Rt, offset, type) \
24 aarch64_insn_gen_comp_branch_imm(0, offset, Rt, A64_VARIANT(sf), \
26 #define A64_CBZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, ZERO)
27 #define A64_CBNZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, NONZERO)
56 #define A64_LS_REG(Rt, Rn, Rm, size, type) \
57 aarch64_insn_gen_load_store_reg(Rt, Rn, Rm, \
70 #define A64_LS_PAIR(Rt, Rt2, Rn, offset, ls, type) \
71 aarch64_insn_gen_load_store_pair(Rt, Rt2, Rn, offset, \
74 /* Rn -= 16; Rn[0] = Rt; Rn[8] = Rt2; */
75 #define A64_PUSH(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, -16, STORE, PRE_INDEX)
76 /* Rt = Rn[0]; Rt2 = Rn[8]; Rn += 16; */
77 #define A64_POP(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, 16, LOAD, POST_INDEX)
82 #define A64_LSX(sf, Rt, Rn, Rs, type) \
83 aarch64_insn_gen_load_store_ex(Rt, Rn, Rs, A64_SIZE(sf), \
85 /* Rt = [Rn]; (atomic) */
86 #define A64_LDXR(sf, Rt, Rn) \
87 A64_LSX(sf, Rt, Rn, A64_ZR, LOAD_EX)
88 /* [Rn] = Rt; (atomic) Rs = [state] */
89 #define A64_STXR(sf, Rt, Rn, Rs) \
90 A64_LSX(sf, Rt, Rn, Rs, STORE_EX)