Lines Matching refs:Rn
51 #define A64_BR(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_NOLINK)
52 #define A64_BLR(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_LINK)
53 #define A64_RET(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_RETURN)
56 #define A64_LS_REG(Rt, Rn, Rm, size, type) \
57 aarch64_insn_gen_load_store_reg(Rt, Rn, Rm, \
70 #define A64_LS_PAIR(Rt, Rt2, Rn, offset, ls, type) \
71 aarch64_insn_gen_load_store_pair(Rt, Rt2, Rn, offset, \
74 /* Rn -= 16; Rn[0] = Rt; Rn[8] = Rt2; */
75 #define A64_PUSH(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, -16, STORE, PRE_INDEX)
76 /* Rt = Rn[0]; Rt2 = Rn[8]; Rn += 16; */
77 #define A64_POP(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, 16, LOAD, POST_INDEX)
82 #define A64_LSX(sf, Rt, Rn, Rs, type) \
83 aarch64_insn_gen_load_store_ex(Rt, Rn, Rs, A64_SIZE(sf), \
85 /* Rt = [Rn]; (atomic) */
86 #define A64_LDXR(sf, Rt, Rn) \
87 A64_LSX(sf, Rt, Rn, A64_ZR, LOAD_EX)
88 /* [Rn] = Rt; (atomic) Rs = [state] */
89 #define A64_STXR(sf, Rt, Rn, Rs) \
90 A64_LSX(sf, Rt, Rn, Rs, STORE_EX)
93 #define A64_STADD(sf, Rn, Rs) \
94 aarch64_insn_gen_stadd(Rn, Rs, A64_SIZE(sf))
97 #define A64_ADDSUB_IMM(sf, Rd, Rn, imm12, type) \
98 aarch64_insn_gen_add_sub_imm(Rd, Rn, imm12, \
100 /* Rd = Rn OP imm12 */
101 #define A64_ADD_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD)
102 #define A64_SUB_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB)
103 #define A64_ADDS_I(sf, Rd, Rn, imm12) \
104 A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD_SETFLAGS)
105 #define A64_SUBS_I(sf, Rd, Rn, imm12) \
106 A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB_SETFLAGS)
107 /* Rn + imm12; set condition flags */
108 #define A64_CMN_I(sf, Rn, imm12) A64_ADDS_I(sf, A64_ZR, Rn, imm12)
109 /* Rn - imm12; set condition flags */
110 #define A64_CMP_I(sf, Rn, imm12) A64_SUBS_I(sf, A64_ZR, Rn, imm12)
111 /* Rd = Rn */
112 #define A64_MOV(sf, Rd, Rn) A64_ADD_I(sf, Rd, Rn, 0)
115 #define A64_BITFIELD(sf, Rd, Rn, immr, imms, type) \
116 aarch64_insn_gen_bitfield(Rd, Rn, immr, imms, \
119 #define A64_SBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, SIGNED)
121 #define A64_UBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, UNSIGNED)
123 /* Rd = Rn << shift */
124 #define A64_LSL(sf, Rd, Rn, shift) ({ \
126 A64_UBFM(sf, Rd, Rn, (unsigned)-(shift) % sz, sz - 1 - (shift)); \
128 /* Rd = Rn >> shift */
129 #define A64_LSR(sf, Rd, Rn, shift) A64_UBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31)
130 /* Rd = Rn >> shift; signed */
131 #define A64_ASR(sf, Rd, Rn, shift) A64_SBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31)
134 #define A64_UXTH(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 15)
135 #define A64_UXTW(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 31)
149 #define A64_ADDSUB_SREG(sf, Rd, Rn, Rm, type) \
150 aarch64_insn_gen_add_sub_shifted_reg(Rd, Rn, Rm, 0, \
152 /* Rd = Rn OP Rm */
153 #define A64_ADD(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, ADD)
154 #define A64_SUB(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB)
155 #define A64_SUBS(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB_SETFLAGS)
158 /* Rn - Rm; set condition flags */
159 #define A64_CMP(sf, Rn, Rm) A64_SUBS(sf, A64_ZR, Rn, Rm)
162 #define A64_DATA1(sf, Rd, Rn, type) aarch64_insn_gen_data1(Rd, Rn, \
164 /* Rd = BSWAPx(Rn) */
165 #define A64_REV16(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_16)
166 #define A64_REV32(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_32)
167 #define A64_REV64(Rd, Rn) A64_DATA1(1, Rd, Rn, REVERSE_64)
170 /* Rd = Rn OP Rm */
171 #define A64_DATA2(sf, Rd, Rn, Rm, type) aarch64_insn_gen_data2(Rd, Rn, Rm, \
173 #define A64_UDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, UDIV)
174 #define A64_LSLV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSLV)
175 #define A64_LSRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSRV)
176 #define A64_ASRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, ASRV)
179 /* Rd = Ra + Rn * Rm */
180 #define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
182 /* Rd = Ra - Rn * Rm */
183 #define A64_MSUB(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
185 /* Rd = Rn * Rm */
186 #define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm)
189 #define A64_LOGIC_SREG(sf, Rd, Rn, Rm, type) \
190 aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
192 /* Rd = Rn OP Rm */
193 #define A64_AND(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND)
194 #define A64_ORR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR)
195 #define A64_EOR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)
196 #define A64_ANDS(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND_SETFLAGS)
197 /* Rn & Rm; set condition flags */
198 #define A64_TST(sf, Rn, Rm) A64_ANDS(sf, A64_ZR, Rn, Rm)
201 #define A64_LOGIC_IMM(sf, Rd, Rn, imm, type) ({ \
204 A64_VARIANT(sf), Rn, Rd, imm64); \
206 /* Rd = Rn OP imm */
207 #define A64_AND_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, AND)
208 #define A64_ORR_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, ORR)
209 #define A64_EOR_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, EOR)
210 #define A64_ANDS_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, AND_SETFLAGS)
211 /* Rn & imm; set condition flags */
212 #define A64_TST_I(sf, Rn, imm) A64_ANDS_I(sf, A64_ZR, Rn, imm)