Lines Matching refs:val
14 static inline void vgic_v2_write_lr(int lr, u32 val)
18 writel_relaxed(val, base + GICH_LR0 + (lr * 4));
60 u32 val = cpuif->vgic_lr[lr];
61 u32 cpuid, intid = val & GICH_LR_VIRTUALID;
65 cpuid = val & GICH_LR_PHYSID_CPUID;
70 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
79 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
86 (val & GICH_LR_PENDING_BIT)) {
96 if (irq->config == VGIC_CONFIG_LEVEL && !(val & GICH_LR_STATE))
112 if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT)) {
139 u32 val = irq->intid;
143 val |= GICH_LR_ACTIVE_BIT;
145 val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT;
148 val |= GICH_LR_EOI;
153 val |= GICH_LR_GROUP1;
156 val |= GICH_LR_HW;
157 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
167 val |= GICH_LR_EOI;
179 val |= GICH_LR_PENDING_BIT;
191 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
195 val |= GICH_LR_EOI;
206 if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT))
210 val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
212 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;