Lines Matching defs:vmcr
267 struct vgic_vmcr vmcr;
270 vgic_get_vmcr(vcpu, &vmcr);
274 val = vmcr.grpen0 << GIC_CPU_CTRL_EnableGrp0_SHIFT;
275 val |= vmcr.grpen1 << GIC_CPU_CTRL_EnableGrp1_SHIFT;
276 val |= vmcr.ackctl << GIC_CPU_CTRL_AckCtl_SHIFT;
277 val |= vmcr.fiqen << GIC_CPU_CTRL_FIQEn_SHIFT;
278 val |= vmcr.cbpr << GIC_CPU_CTRL_CBPR_SHIFT;
279 val |= vmcr.eoim << GIC_CPU_CTRL_EOImodeNS_SHIFT;
290 val = (vmcr.pmr & GICV_PMR_PRIORITY_MASK) >>
294 val = vmcr.bpr;
297 val = vmcr.abpr;
315 struct vgic_vmcr vmcr;
317 vgic_get_vmcr(vcpu, &vmcr);
321 vmcr.grpen0 = !!(val & GIC_CPU_CTRL_EnableGrp0);
322 vmcr.grpen1 = !!(val & GIC_CPU_CTRL_EnableGrp1);
323 vmcr.ackctl = !!(val & GIC_CPU_CTRL_AckCtl);
324 vmcr.fiqen = !!(val & GIC_CPU_CTRL_FIQEn);
325 vmcr.cbpr = !!(val & GIC_CPU_CTRL_CBPR);
326 vmcr.eoim = !!(val & GIC_CPU_CTRL_EOImodeNS);
337 vmcr.pmr = (val << GICV_PMR_PRIORITY_SHIFT) &
341 vmcr.bpr = val;
344 vmcr.abpr = val;
348 vgic_set_vmcr(vcpu, &vmcr);