Lines Matching defs:vmcr
18 struct vgic_vmcr vmcr;
21 vgic_get_vmcr(vcpu, &vmcr);
60 vmcr.cbpr = (val & ICC_CTLR_EL1_CBPR_MASK) >> ICC_CTLR_EL1_CBPR_SHIFT;
61 vmcr.eoim = (val & ICC_CTLR_EL1_EOImode_MASK) >> ICC_CTLR_EL1_EOImode_SHIFT;
62 vgic_set_vmcr(vcpu, &vmcr);
78 val |= (vmcr.cbpr << ICC_CTLR_EL1_CBPR_SHIFT) & ICC_CTLR_EL1_CBPR_MASK;
79 val |= (vmcr.eoim << ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;
90 struct vgic_vmcr vmcr;
92 vgic_get_vmcr(vcpu, &vmcr);
94 vmcr.pmr = (p->regval & ICC_PMR_EL1_MASK) >> ICC_PMR_EL1_SHIFT;
95 vgic_set_vmcr(vcpu, &vmcr);
97 p->regval = (vmcr.pmr << ICC_PMR_EL1_SHIFT) & ICC_PMR_EL1_MASK;
106 struct vgic_vmcr vmcr;
108 vgic_get_vmcr(vcpu, &vmcr);
110 vmcr.bpr = (p->regval & ICC_BPR0_EL1_MASK) >>
112 vgic_set_vmcr(vcpu, &vmcr);
114 p->regval = (vmcr.bpr << ICC_BPR0_EL1_SHIFT) &
124 struct vgic_vmcr vmcr;
129 vgic_get_vmcr(vcpu, &vmcr);
130 if (!vmcr.cbpr) {
132 vmcr.abpr = (p->regval & ICC_BPR1_EL1_MASK) >>
134 vgic_set_vmcr(vcpu, &vmcr);
136 p->regval = (vmcr.abpr << ICC_BPR1_EL1_SHIFT) &
141 p->regval = min((vmcr.bpr + 1), 7U);
150 struct vgic_vmcr vmcr;
152 vgic_get_vmcr(vcpu, &vmcr);
154 vmcr.grpen0 = (p->regval & ICC_IGRPEN0_EL1_MASK) >>
156 vgic_set_vmcr(vcpu, &vmcr);
158 p->regval = (vmcr.grpen0 << ICC_IGRPEN0_EL1_SHIFT) &
168 struct vgic_vmcr vmcr;
170 vgic_get_vmcr(vcpu, &vmcr);
172 vmcr.grpen1 = (p->regval & ICC_IGRPEN1_EL1_MASK) >>
174 vgic_set_vmcr(vcpu, &vmcr);
176 p->regval = (vmcr.grpen1 << ICC_IGRPEN1_EL1_SHIFT) &