Lines Matching defs:val
19 u64 val;
23 val = p->regval;
29 host_pri_bits = ((val & ICC_CTLR_EL1_PRI_BITS_MASK) >>
36 host_id_bits = (val & ICC_CTLR_EL1_ID_BITS_MASK) >>
45 seis = (val & ICC_CTLR_EL1_SEIS_MASK) >>
52 a3v = (val & ICC_CTLR_EL1_A3V_MASK) >> ICC_CTLR_EL1_A3V_SHIFT;
60 vmcr.cbpr = (val & ICC_CTLR_EL1_CBPR_MASK) >> ICC_CTLR_EL1_CBPR_SHIFT;
61 vmcr.eoim = (val & ICC_CTLR_EL1_EOImode_MASK) >> ICC_CTLR_EL1_EOImode_SHIFT;
64 val = 0;
65 val |= (vgic_v3_cpu->num_pri_bits - 1) <<
67 val |= vgic_v3_cpu->num_id_bits << ICC_CTLR_EL1_ID_BITS_SHIFT;
68 val |= ((kvm_vgic_global_state.ich_vtr_el2 &
71 val |= ((kvm_vgic_global_state.ich_vtr_el2 &
78 val |= (vmcr.cbpr << ICC_CTLR_EL1_CBPR_SHIFT) & ICC_CTLR_EL1_CBPR_MASK;
79 val |= (vmcr.eoim << ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;
81 p->regval = val;