Lines Matching refs:lr_val
438 u64 *lr_val)
466 *lr_val = val;
471 *lr_val = ICC_IAR1_EL1_SPURIOUS;
477 u64 *lr_val)
487 *lr_val = val;
492 *lr_val = ICC_IAR1_EL1_SPURIOUS;
629 u64 lr_val;
635 lr = __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
639 if (grp != !!(lr_val & ICH_LR_GROUP))
643 lr_prio = (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
650 lr_val &= ~ICH_LR_STATE;
652 if ((lr_val & ICH_LR_VIRTUAL_ID_MASK) <= VGIC_MAX_SPI)
653 lr_val |= ICH_LR_ACTIVE_BIT;
654 __gic_v3_set_lr(lr_val, lr);
656 vcpu_set_reg(vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);
663 static void __vgic_v3_clear_active_lr(int lr, u64 lr_val)
665 lr_val &= ~ICH_LR_ACTIVE_BIT;
666 if (lr_val & ICH_LR_HW) {
669 pid = (lr_val & ICH_LR_PHYS_ID_MASK) >> ICH_LR_PHYS_ID_SHIFT;
673 __gic_v3_set_lr(lr_val, lr);
688 u64 lr_val;
699 lr = __vgic_v3_find_active_lr(vcpu, vid, &lr_val);
705 __vgic_v3_clear_active_lr(lr, lr_val);
711 u64 lr_val;
728 lr = __vgic_v3_find_active_lr(vcpu, vid, &lr_val);
734 lr_prio = (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
737 if (grp != !!(lr_val & ICH_LR_GROUP) ||
742 __vgic_v3_clear_active_lr(lr, lr_val);
892 u64 lr_val;
897 lr = __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
901 lr_grp = !!(lr_val & ICH_LR_GROUP);
903 lr_val = ICC_IAR1_EL1_SPURIOUS;
906 vcpu_set_reg(vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);