Lines Matching refs:insn
24 t32_simulate_table_branch(probes_opcode_t insn,
28 int rn = (insn >> 16) & 0xf;
29 int rm = insn & 0xf;
35 if (insn & 0x10) /* TBH */
44 t32_simulate_mrs(probes_opcode_t insn,
47 int rd = (insn >> 8) & 0xf;
53 t32_simulate_cond_branch(probes_opcode_t insn,
58 long offset = insn & 0x7ff; /* imm11 */
59 offset += (insn & 0x003f0000) >> 5; /* imm6 */
60 offset += (insn & 0x00002000) << 4; /* J1 */
61 offset += (insn & 0x00000800) << 7; /* J2 */
62 offset -= (insn & 0x04000000) >> 7; /* Apply sign bit */
68 t32_decode_cond_branch(probes_opcode_t insn, struct arch_probes_insn *asi,
71 int cc = (insn >> 22) & 0xf;
78 t32_simulate_branch(probes_opcode_t insn,
83 long offset = insn & 0x7ff; /* imm11 */
84 offset += (insn & 0x03ff0000) >> 5; /* imm10 */
85 offset += (insn & 0x00002000) << 9; /* J1 */
86 offset += (insn & 0x00000800) << 10; /* J2 */
87 if (insn & 0x04000000)
92 if (insn & (1 << 14)) {
95 if (!(insn & (1 << 12))) {
106 t32_simulate_ldr_literal(probes_opcode_t insn,
110 int rt = (insn >> 12) & 0xf;
113 long offset = insn & 0xfff;
114 if (insn & 0x00800000)
119 if (insn & 0x00400000) {
126 } else if (insn & 0x00200000) {
128 if (insn & 0x01000000)
134 if (insn & 0x01000000)
144 t32_decode_ldmstm(probes_opcode_t insn, struct arch_probes_insn *asi,
147 enum probes_insn ret = kprobe_decode_ldmstm(insn, asi, d);
150 insn = __mem_to_opcode_arm(asi->insn[0]);
151 ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(insn >> 16);
152 ((u16 *)asi->insn)[1] = __opcode_to_mem_thumb16(insn & 0xffff);
158 t32_emulate_ldrdstrd(probes_opcode_t insn,
162 int rt1 = (insn >> 12) & 0xf;
163 int rt2 = (insn >> 8) & 0xf;
164 int rn = (insn >> 16) & 0xf;
185 t32_emulate_ldrstr(probes_opcode_t insn,
188 int rt = (insn >> 12) & 0xf;
189 int rn = (insn >> 16) & 0xf;
190 int rm = insn & 0xf;
211 t32_emulate_rd8rn16rm0_rwflags(probes_opcode_t insn,
214 int rd = (insn >> 8) & 0xf;
215 int rn = (insn >> 16) & 0xf;
216 int rm = insn & 0xf;
238 t32_emulate_rd8pc16_noflags(probes_opcode_t insn,
242 int rd = (insn >> 8) & 0xf;
258 t32_emulate_rd8rn16_noflags(probes_opcode_t insn,
261 int rd = (insn >> 8) & 0xf;
262 int rn = (insn >> 16) & 0xf;
278 t32_emulate_rdlo12rdhi8rn16rm0_noflags(probes_opcode_t insn,
282 int rdlo = (insn >> 12) & 0xf;
283 int rdhi = (insn >> 8) & 0xf;
284 int rn = (insn >> 16) & 0xf;
285 int rm = insn & 0xf;
306 t16_simulate_bxblx(probes_opcode_t insn,
310 int rm = (insn >> 3) & 0xf;
313 if (insn & (1 << 7)) /* BLX ? */
320 t16_simulate_ldr_literal(probes_opcode_t insn,
324 long index = insn & 0xff;
325 int rt = (insn >> 8) & 0x7;
330 t16_simulate_ldrstr_sp_relative(probes_opcode_t insn,
334 long index = insn & 0xff;
335 int rt = (insn >> 8) & 0x7;
336 if (insn & 0x800) /* LDR */
343 t16_simulate_reladr(probes_opcode_t insn,
346 unsigned long base = (insn & 0x800) ? regs->ARM_sp
348 long offset = insn & 0xff;
349 int rt = (insn >> 8) & 0x7;
354 t16_simulate_add_sp_imm(probes_opcode_t insn,
357 long imm = insn & 0x7f;
358 if (insn & 0x80) /* SUB */
365 t16_simulate_cbz(probes_opcode_t insn,
368 int rn = insn & 0x7;
369 probes_opcode_t nonzero = regs->uregs[rn] ? insn : ~insn;
371 long i = insn & 0x200;
372 long imm5 = insn & 0xf8;
379 t16_simulate_it(probes_opcode_t insn,
386 * The new IT state is in the lower byte of insn.
390 cpsr |= (insn & 0xfc) << 8;
391 cpsr |= (insn & 0x03) << 25;
396 t16_singlestep_it(probes_opcode_t insn,
400 t16_simulate_it(insn, asi, regs);
404 t16_decode_it(probes_opcode_t insn, struct arch_probes_insn *asi,
412 t16_simulate_cond_branch(probes_opcode_t insn,
416 long offset = insn & 0x7f;
417 offset -= insn & 0x80; /* Apply sign bit */
422 t16_decode_cond_branch(probes_opcode_t insn, struct arch_probes_insn *asi,
425 int cc = (insn >> 8) & 0xf;
432 t16_simulate_branch(probes_opcode_t insn,
436 long offset = insn & 0x3ff;
437 offset -= insn & 0x400; /* Apply sign bit */
442 t16_emulate_loregs(probes_opcode_t insn,
465 t16_emulate_loregs_rwflags(probes_opcode_t insn,
468 regs->ARM_cpsr = t16_emulate_loregs(insn, asi, regs);
472 t16_emulate_loregs_noitrwflags(probes_opcode_t insn,
475 unsigned long cpsr = t16_emulate_loregs(insn, asi, regs);
481 t16_emulate_hiregs(probes_opcode_t insn,
485 int rdn = (insn & 0x7) | ((insn & 0x80) >> 4);
486 int rm = (insn >> 3) & 0xf;
512 t16_decode_hiregs(probes_opcode_t insn, struct arch_probes_insn *asi,
515 insn &= ~0x00ff;
516 insn |= 0x001; /* Set Rdn = R1 and Rm = R0 */
517 ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(insn);
523 t16_emulate_push(probes_opcode_t insn,
540 t16_decode_push(probes_opcode_t insn, struct arch_probes_insn *asi,
549 ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(0xe929);
551 ((u16 *)asi->insn)[1] = __opcode_to_mem_thumb16(insn & 0x1ff);
557 t16_emulate_pop_nopc(probes_opcode_t insn,
574 t16_emulate_pop_pc(probes_opcode_t insn,
595 t16_decode_pop(probes_opcode_t insn, struct arch_probes_insn *asi,
604 ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(0xe8b9);
606 ((u16 *)asi->insn)[1] = __opcode_to_mem_thumb16(insn & 0x1ff);
607 asi->insn_handler = insn & 0x100 ? t16_emulate_pop_pc