Lines Matching refs:ldr
75 ldr \rd, [\base, #EMC_ADR_CFG]
85 ldr \rd, [\base, #EMC_EMC_STATUS]
91 ldr \rd, [\r_car_base, #\pll_base]
97 ldr \rd, [\r_car_base, #\pll_misc]
100 ldr \rd, [\r_car_base, #\pll_misc]
101 ldr \rd, [\r_car_base, #\pll_misc]
109 ldr \rd, [\r_car_base, #\pll_base]
115 ldr \rd, [\car, #\iddq]
121 ldr \rd, [\car, #\iddq]
159 ldr r12, =TEGRA_FLOW_CTRL_VIRT
186 ldr r3, [r1] @ read CSR
205 ldr r0, [r2]
339 ldr r1, [r7]
345 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
358 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
385 ldr r1, [r0, #CLK_RESET_PLLP_BASE]
394 ldr r1, [r7]
400 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
403 ldr r4, [r5, #0x1C] @ restore SCLK_BURST
411 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
428 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
430 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
432 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
436 ldr r1, [r0, #EMC_CFG_DIG_DLL]
447 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
453 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
457 ldr r1, [r0, #EMC_CFG]
471 ldr r2, [r0, #EMC_EMC_STATUS]
478 ldr r2, [r0, #EMC_FBIO_CFG5]
487 ldr r2, [r7]
497 ldr r2, [r7]
506 ldr r2, [r7]
516 ldr r2, [r7]
523 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
525 ldr r1, [r5, #0x0] @ restore EMC_CFG
541 ldr r0, [r0, #PMC_SCRATCH41]
626 ldr r1, [r7]
635 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
640 ldr r1, [r7]
645 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
652 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
660 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
663 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
666 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
697 ldr r0, [r6, r2]
711 ldr r0, [r6, r2] /* memory barrier */
751 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
753 ldr r1, [r0]
775 ldr r1, [r0, #EMC_CFG]
782 ldr r1, [r7]
787 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
795 ldr r1, [r0, #EMC_EMC_STATUS]
805 ldr r2, [r0, #EMC_EMC_STATUS]
811 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
815 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
832 ldr r1, [r4, #PMC_CTRL]