Lines Matching refs:Div
341 #define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
342 (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
344 #define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
345 (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
347 /* fua = fxtl/(16*Floor (Div/16)) */
348 /* Tua = 16*Floor (Div/16)*Txtl */
349 #define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
350 (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
352 #define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
353 (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
355 /* fua = fxtl/(16*Ceil (Div/16)) */
356 /* Tua = 16*Ceil (Div/16)*Txtl */
480 #define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
481 (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
483 #define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
484 (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
486 /* fsd = fxtl/(16*Floor (Div/16)) */
487 /* Tsd = 16*Floor (Div/16)*Txtl */
488 #define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
489 (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
491 #define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
492 (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
494 /* fsd = fxtl/(16*Ceil (Div/16)) */
495 /* Tsd = 16*Ceil (Div/16)*Txtl */
641 #define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \
643 ((Div)/32 << FShft (MCCR0_ASD))
644 /* faud = fmc/(32*Floor (Div/32)) */
645 /* Taud = 32*Floor (Div/32)*Tmc */
646 #define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \
647 (((Div) + 31)/32 << FShft (MCCR0_ASD))
648 /* faud = fmc/(32*Ceil (Div/32)) */
649 /* Taud = 32*Ceil (Div/32)*Tmc */
654 #define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \
656 ((Div)/32 << FShft (MCCR0_TSD))
657 /* ftcm = fmc/(32*Floor (Div/32)) */
658 /* Ttcm = 32*Floor (Div/32)*Tmc */
659 #define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \
660 (((Div) + 31)/32 << FShft (MCCR0_TSD))
661 /* ftcm = fmc/(32*Ceil (Div/32)) */
662 /* Ttcm = 32*Ceil (Div/32)*Tmc */
681 #define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \
682 (((Div) - 1) << FShft (MCCR0_ECP))
774 #define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \
775 (((Div) - 2)/2 << FShft (SSCR0_SCR))
776 /* fss = fxtl/(2*Floor (Div/2)) */
777 /* Tss = 2*Floor (Div/2)*Txtl */
778 #define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \
779 (((Div) - 1)/2 << FShft (SSCR0_SCR))
780 /* fss = fxtl/(2*Ceil (Div/2)) */
781 /* Tss = 2*Ceil (Div/2)*Txtl */
1754 #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \
1755 (((Div) - 4)/2 << FShft (LCCR3_PCD))
1756 /* fpix = fcpu/(2*Floor (Div/2)) */
1757 /* Tpix = 2*Floor (Div/2)*Tcpu */
1758 #define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \
1759 (((Div) - 3)/2 << FShft (LCCR3_PCD))
1760 /* fpix = fcpu/(2*Ceil (Div/2)) */
1761 /* Tpix = 2*Ceil (Div/2)*Tcpu */
1764 #define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \
1765 (((Div) - 2)/2 << FShft (LCCR3_ACB))
1766 /* fac = fln/(2*Floor (Div/2)) */
1767 /* Tac = 2*Floor (Div/2)*Tln */
1768 #define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \
1769 (((Div) - 1)/2 << FShft (LCCR3_ACB))
1770 /* fac = fln/(2*Ceil (Div/2)) */
1771 /* Tac = 2*Ceil (Div/2)*Tln */