Lines Matching refs:x02
83 #define S3C2410_GPB0_TOUT0 (0x02 << 0)
85 #define S3C2410_GPB1_TOUT1 (0x02 << 2)
87 #define S3C2410_GPB2_TOUT2 (0x02 << 4)
89 #define S3C2410_GPB3_TOUT3 (0x02 << 6)
91 #define S3C2410_GPB4_TCLK0 (0x02 << 8)
94 #define S3C2410_GPB5_nXBACK (0x02 << 10)
97 #define S3C2410_GPB6_nXBREQ (0x02 << 12)
100 #define S3C2410_GPB7_nXDACK1 (0x02 << 14)
103 #define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
105 #define S3C2410_GPB9_nXDACK0 (0x02 << 18)
108 #define S3C2410_GPB10_nXDRE0 (0x02 << 20)
122 #define S3C2410_GPC0_LEND (0x02 << 0)
123 #define S3C2410_GPC1_VCLK (0x02 << 2)
124 #define S3C2410_GPC2_VLINE (0x02 << 4)
125 #define S3C2410_GPC3_VFRAME (0x02 << 6)
126 #define S3C2410_GPC4_VM (0x02 << 8)
127 #define S3C2410_GPC5_LCDVF0 (0x02 << 10)
128 #define S3C2410_GPC6_LCDVF1 (0x02 << 12)
129 #define S3C2410_GPC7_LCDVF2 (0x02 << 14)
130 #define S3C2410_GPC8_VD0 (0x02 << 16)
131 #define S3C2410_GPC9_VD1 (0x02 << 18)
132 #define S3C2410_GPC10_VD2 (0x02 << 20)
133 #define S3C2410_GPC11_VD3 (0x02 << 22)
134 #define S3C2410_GPC12_VD4 (0x02 << 24)
135 #define S3C2410_GPC13_VD5 (0x02 << 26)
136 #define S3C2410_GPC14_VD6 (0x02 << 28)
137 #define S3C2410_GPC15_VD7 (0x02 << 30)
153 #define S3C2410_GPD0_VD8 (0x02 << 0)
156 #define S3C2410_GPD1_VD9 (0x02 << 2)
159 #define S3C2410_GPD2_VD10 (0x02 << 4)
161 #define S3C2410_GPD3_VD11 (0x02 << 6)
163 #define S3C2410_GPD4_VD12 (0x02 << 8)
165 #define S3C2410_GPD5_VD13 (0x02 << 10)
167 #define S3C2410_GPD6_VD14 (0x02 << 12)
169 #define S3C2410_GPD7_VD15 (0x02 << 14)
171 #define S3C2410_GPD8_VD16 (0x02 << 16)
174 #define S3C2410_GPD9_VD17 (0x02 << 18)
177 #define S3C2410_GPD10_VD18 (0x02 << 20)
180 #define S3C2410_GPD11_VD19 (0x02 << 22)
182 #define S3C2410_GPD12_VD20 (0x02 << 24)
184 #define S3C2410_GPD13_VD21 (0x02 << 26)
186 #define S3C2410_GPD14_VD22 (0x02 << 28)
189 #define S3C2410_GPD15_VD23 (0x02 << 30)
207 #define S3C2410_GPE0_I2SLRCK (0x02 << 0)
211 #define S3C2410_GPE1_I2SSCLK (0x02 << 2)
215 #define S3C2410_GPE2_CDCLK (0x02 << 4)
218 #define S3C2410_GPE3_I2SSDI (0x02 << 6)
223 #define S3C2410_GPE4_I2SSDO (0x02 << 8)
228 #define S3C2410_GPE5_SDCLK (0x02 << 10)
229 #define S3C2443_GPE5_SD1_CLK (0x02 << 10)
232 #define S3C2410_GPE6_SDCMD (0x02 << 12)
233 #define S3C2443_GPE6_SD1_CMD (0x02 << 12)
236 #define S3C2410_GPE7_SDDAT0 (0x02 << 14)
237 #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
240 #define S3C2410_GPE8_SDDAT1 (0x02 << 16)
241 #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
244 #define S3C2410_GPE9_SDDAT2 (0x02 << 18)
245 #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
248 #define S3C2410_GPE10_SDDAT3 (0x02 << 20)
249 #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
251 #define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
253 #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
255 #define S3C2410_GPE13_SPICLK0 (0x02 << 26)
257 #define S3C2410_GPE14_IICSCL (0x02 << 28)
260 #define S3C2410_GPE15_IICSDA (0x02 << 30)
288 #define S3C2410_GPF0_EINT0 (0x02 << 0)
289 #define S3C2410_GPF1_EINT1 (0x02 << 2)
290 #define S3C2410_GPF2_EINT2 (0x02 << 4)
291 #define S3C2410_GPF3_EINT3 (0x02 << 6)
292 #define S3C2410_GPF4_EINT4 (0x02 << 8)
293 #define S3C2410_GPF5_EINT5 (0x02 << 10)
294 #define S3C2410_GPF6_EINT6 (0x02 << 12)
295 #define S3C2410_GPF7_EINT7 (0x02 << 14)
311 #define S3C2410_GPG0_EINT8 (0x02 << 0)
313 #define S3C2410_GPG1_EINT9 (0x02 << 2)
315 #define S3C2410_GPG2_EINT10 (0x02 << 4)
318 #define S3C2410_GPG3_EINT11 (0x02 << 6)
321 #define S3C2410_GPG4_EINT12 (0x02 << 8)
325 #define S3C2410_GPG5_EINT13 (0x02 << 10)
328 #define S3C2410_GPG6_EINT14 (0x02 << 12)
331 #define S3C2410_GPG7_EINT15 (0x02 << 14)
334 #define S3C2410_GPG8_EINT16 (0x02 << 16)
336 #define S3C2410_GPG9_EINT17 (0x02 << 18)
338 #define S3C2410_GPG10_EINT18 (0x02 << 20)
340 #define S3C2410_GPG11_EINT19 (0x02 << 22)
344 #define S3C2410_GPG12_EINT20 (0x02 << 24)
349 #define S3C2410_GPG13_EINT21 (0x02 << 26)
353 #define S3C2410_GPG14_EINT22 (0x02 << 28)
357 #define S3C2410_GPG15_EINT23 (0x02 << 30)
375 #define S3C2410_GPH0_nCTS0 (0x02 << 0)
376 #define S3C2416_GPH0_TXD0 (0x02 << 0)
378 #define S3C2410_GPH1_nRTS0 (0x02 << 2)
379 #define S3C2416_GPH1_RXD0 (0x02 << 2)
381 #define S3C2410_GPH2_TXD0 (0x02 << 4)
382 #define S3C2416_GPH2_TXD1 (0x02 << 4)
384 #define S3C2410_GPH3_RXD0 (0x02 << 6)
385 #define S3C2416_GPH3_RXD1 (0x02 << 6)
387 #define S3C2410_GPH4_TXD1 (0x02 << 8)
388 #define S3C2416_GPH4_TXD2 (0x02 << 8)
390 #define S3C2410_GPH5_RXD1 (0x02 << 10)
391 #define S3C2416_GPH5_RXD2 (0x02 << 10)
393 #define S3C2410_GPH6_TXD2 (0x02 << 12)
394 #define S3C2416_GPH6_TXD3 (0x02 << 12)
398 #define S3C2410_GPH7_RXD2 (0x02 << 14)
399 #define S3C2416_GPH7_RXD3 (0x02 << 14)
403 #define S3C2410_GPH8_UCLK (0x02 << 16)
404 #define S3C2416_GPH8_nCTS0 (0x02 << 16)
406 #define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
408 #define S3C2416_GPH9_nRTS0 (0x02 << 18)
410 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
411 #define S3C2416_GPH10_nCTS1 (0x02 << 20)
413 #define S3C2416_GPH11_nRTS1 (0x02 << 22)
415 #define S3C2416_GPH12_EXTUARTCLK (0x02 << 24)
417 #define S3C2416_GPH13_CLKOUT0 (0x02 << 26)
419 #define S3C2416_GPH14_CLKOUT1 (0x02 << 28)
592 #define S3C2412_GPIO_SLPCON_IN ( 0x02 )
597 #define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
599 #define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */