Lines Matching refs:writel_relaxed
69 writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
70 writel_relaxed(0, base + SCSS_CPU1CORE_RESET);
71 writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP);
114 writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL);
120 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
122 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
127 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
132 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
137 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
142 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
201 writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
208 writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
215 writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
218 writel_relaxed(0x10003, l2_saw_base + APCS_SAW2_2_VCTL);
223 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
228 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
233 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
237 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);