Lines Matching defs:fpga
36 struct cplds *fpga = d;
41 pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask;
43 generic_handle_irq(irq_find_mapping(fpga->irqdomain,
53 struct cplds *fpga = irq_data_get_irq_chip_data(d);
57 fpga->irq_mask &= ~bit;
58 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
63 struct cplds *fpga = irq_data_get_irq_chip_data(d);
67 set = readl(fpga->base + FPGA_IRQ_SET_CLR);
68 writel(set & ~bit, fpga->base + FPGA_IRQ_SET_CLR);
70 fpga->irq_mask |= bit;
71 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
85 struct cplds *fpga = d->host_data;
88 irq_set_chip_data(irq, fpga);
100 struct cplds *fpga = platform_get_drvdata(pdev);
102 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
110 struct cplds *fpga;
115 fpga = devm_kzalloc(&pdev->dev, sizeof(*fpga), GFP_KERNEL);
116 if (!fpga)
119 fpga->irq = platform_get_irq(pdev, 0);
120 if (fpga->irq <= 0)
121 return fpga->irq;
128 fpga->base = devm_ioremap_resource(&pdev->dev, res);
129 if (IS_ERR(fpga->base))
130 return PTR_ERR(fpga->base);
132 platform_set_drvdata(pdev, fpga);
134 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
135 writel(0, fpga->base + FPGA_IRQ_SET_CLR);
137 irqflags = irq_get_trigger_type(fpga->irq);
138 ret = devm_request_irq(&pdev->dev, fpga->irq, cplds_irq_handler,
139 irqflags, dev_name(&pdev->dev), fpga);
145 fpga->irq, ret);
149 irq_set_irq_wake(fpga->irq, 1);
150 fpga->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
152 &cplds_irq_domain_ops, fpga);
153 if (!fpga->irqdomain)
157 ret = irq_create_strict_mappings(fpga->irqdomain, base_irq, 0,
171 struct cplds *fpga = platform_get_drvdata(pdev);
173 irq_set_chip_and_handler(fpga->irq, NULL, NULL);