Lines Matching refs:x0000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
62 #define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000
63 #define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000
68 #define DRA7XX_REVISION_PRM_OFFSET 0x0000
97 #define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET 0x0000
98 #define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000)
207 #define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
212 #define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET 0x0000
219 #define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET 0x0000
240 #define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0000
256 #define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000
323 #define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000
331 #define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000
344 #define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000
353 #define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000
358 #define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
386 #define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET 0x0000
496 #define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000
501 #define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0000
530 #define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000
573 #define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000
578 #define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000
586 #define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET 0x0000
593 #define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET 0x0000
601 #define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET 0x0000
609 #define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET 0x0000
617 #define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET 0x0000
625 #define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET 0x0000
629 #define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET 0x0000
635 #define DRA7XX_PRM_RSTCTRL_OFFSET 0x0000