Lines Matching refs:x0000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
43 #define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000
44 #define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000
51 #define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000
52 #define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000
53 #define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000
54 #define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000
55 #define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000
58 #define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000
59 #define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000
67 #define DRA7XX_REVISION_CM_CORE_OFFSET 0x0000
73 #define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0000
74 #define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000)
133 #define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000
162 #define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000
291 #define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000
300 #define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000
316 #define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000
327 #define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000
334 #define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
372 #define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000
377 #define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0000