Lines Matching refs:rate
54 return clk->parent->rate / div;
132 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
153 realrate = parent->rate;
155 if (realrate <= rate)
169 return clk->parent->rate / dsor;
187 return clk->parent->rate / dsor;
191 int omap1_select_table_rate(struct clk *clk, unsigned long rate)
193 /* Find the highest supported frequency <= rate and switch to it */
197 ref_rate = ck_ref_p->rate;
199 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
207 if (ptr->rate <= rate)
211 if (!ptr->rate)
221 ck_dpll1_p->rate = ptr->pll_rate;
226 int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
231 dsor_exp = calc_dsor_exp(clk, rate);
241 clk->rate = clk->parent->rate / (1 << dsor_exp);
246 long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
248 int dsor_exp = calc_dsor_exp(clk, rate);
253 return clk->parent->rate / (1 << dsor_exp);
256 int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
261 dsor_exp = calc_dsor_exp(clk, rate);
272 clk->rate = clk->parent->rate / (1 << dsor_exp);
276 long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
278 /* Find the highest supported frequency <= rate */
283 ref_rate = ck_ref_p->rate;
287 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
294 highest_rate = ptr->rate;
297 if (ptr->rate <= rate)
304 static unsigned calc_ext_dsor(unsigned long rate)
320 if (rate >= 96000000 / dsor)
327 int omap1_set_uart_rate(struct clk *clk, unsigned long rate)
332 if (rate == 12000000)
334 else if (rate == 48000000)
339 clk->rate = rate;
345 int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate)
350 dsor = calc_ext_dsor(rate);
351 clk->rate = 96000000 / dsor;
363 int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
369 p_rate = clk->parent->rate;
371 div = (p_rate + rate - 1) / rate;
381 clk->rate = p_rate / (div + 1);
386 long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate)
388 return 96000000 / calc_ext_dsor(rate);
396 /* Determine current rate and ensure clock is based on 96MHz APLL */
406 clk-> rate = 96000000 / dsor;
558 long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
561 return clk->round_rate(clk, rate);
563 return clk->rate;
566 int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
571 ret = clk->set_rate(clk, rate);
657 ret = clk->rate;
668 long clk_round_rate(struct clk *clk, unsigned long rate)
677 ret = omap1_clk_round_rate(clk, rate);
684 int clk_set_rate(struct clk *clk, unsigned long rate)
693 ret = omap1_clk_set_rate(clk, rate);
723 return clk->parent->rate;
734 return clk->parent->rate / clk->fixed_div;
748 /* Propagate rate to children */
755 clkp->rate = clkp->recalc(clkp);
775 clkp->rate = clkp->recalc(clkp);
975 "clock-name", "parent-name", "rate", "use-count");
980 c->name, pa ? pa->name : "none", c->rate,
999 debugfs_create_ulong("rate", S_IRUGO, c->dent, &c->rate);