Lines Matching defs:ICU_REG
12 #define ICU_REG(x) (ICU_VIRT_BASE + (x))
17 #define ICU_INT_CONF(n) ICU_REG((n) << 2)
25 #define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */
26 #define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */
27 #define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */
28 #define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */
29 #define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */
41 #define MMP2_ICU_PJ4_IRQ_STATUS0 ICU_REG(0x138)
42 #define MMP2_ICU_PJ4_IRQ_STATUS1 ICU_REG(0x13c)
43 #define MMP2_ICU_PJ4_FIQ_STATUS0 ICU_REG(0x140)
44 #define MMP2_ICU_PJ4_FIQ_STATUS1 ICU_REG(0x144)
46 #define MMP2_ICU_INT4_STATUS ICU_REG(0x150)
47 #define MMP2_ICU_INT5_STATUS ICU_REG(0x154)
48 #define MMP2_ICU_INT17_STATUS ICU_REG(0x158)
49 #define MMP2_ICU_INT35_STATUS ICU_REG(0x15c)
50 #define MMP2_ICU_INT51_STATUS ICU_REG(0x160)
52 #define MMP2_ICU_INT4_MASK ICU_REG(0x168)
53 #define MMP2_ICU_INT5_MASK ICU_REG(0x16C)
54 #define MMP2_ICU_INT17_MASK ICU_REG(0x170)
55 #define MMP2_ICU_INT35_MASK ICU_REG(0x174)
56 #define MMP2_ICU_INT51_MASK ICU_REG(0x178)
58 #define MMP2_ICU_SP_IRQ_SEL ICU_REG(0x100)
59 #define MMP2_ICU_PJ4_IRQ_SEL ICU_REG(0x104)
60 #define MMP2_ICU_PJ4_FIQ_SEL ICU_REG(0x108)
62 #define MMP2_ICU_INVERT ICU_REG(0x164)