Lines Matching refs:WORK2_REG
18 #define WORK2_REG r1
55 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
56 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
57 cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
60 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
61 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
62 cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
68 orr WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
69 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
75 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
76 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
77 cmp WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
88 and WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK
89 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
94 bic WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
95 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
111 ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
112 and WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
133 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
134 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH