Lines Matching defs:CLKPWRBASE_REG
23 #define CLKPWRBASE_REG r6
45 ldr CLKPWRBASE_REG, [WORK1_REG, #0]
48 ldr SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
67 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
69 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
70 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
82 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
86 ldr SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
89 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
92 ldr SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
95 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
99 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
108 str SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
111 ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
117 str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
121 str SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
127 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
128 str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\