Lines Matching refs:ldr
76 ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
82 ldr r6, [r11, #L2X0_CACHE_SYNC]
97 ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
98 ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
101 ldr r8, [r7], #0x4
102 ldr r9, [r7], #0x4
115 ldr r7, =MX6Q_MMDC_MPDGCTRL0
116 ldr r6, [r11, r7]
120 ldr r6, [r11, r7]
125 ldr r6, [r11, r7]
129 ldr r6, [r11, r7]
134 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
138 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
143 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
150 ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
151 ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
152 ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
153 ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
159 ldr r6, =imx6_suspend
160 ldr r7, =resume
170 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
171 ldr r6, [r11, #0x0]
172 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
173 ldr r6, [r11, #0x0]
174 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
175 ldr r6, [r11, #0x0]
178 ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
186 ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
191 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
196 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
201 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
205 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
206 ldr r6, =0x0
207 ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
208 ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET
214 ldr r9, [r8], #0x8
221 ldr r6, =0x1000
222 ldr r9, [r8], #0x8
224 ldr r9, [r8], #0x8
226 ldr r6, =0x80000
227 ldr r9, [r8]
238 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
239 ldr r6, [r11, #MX6Q_GPC_IMR1]
240 ldr r7, [r11, #MX6Q_GPC_IMR2]
241 ldr r8, [r11, #MX6Q_GPC_IMR3]
242 ldr r9, [r11, #MX6Q_GPC_IMR4]
244 ldr r10, =0xffffffff
256 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
257 ldr r10, [r11, #MX6Q_CCM_CCR]
263 ldr r10, [r11, #MX6Q_CCM_CCR]
268 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
284 ldr r6, =2000
318 ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
320 ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
325 ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]