Lines Matching refs:rp
45 #define checkuart(rp, rv, family_id, family) \
47 ldr rp, =family_id ; \
49 cmp rp, rv ; \
51 ldreq rp, =UARTA_##family ; \
55 .macro addruart, rp, rv, tmp
56 adr \rp, 99f @ actual addr of 99f
57 ldr \rv, [\rp] @ linked addr is stored there
58 sub \rv, \rv, \rp @ offset between the two
59 ldr \rp, [\rp, #4] @ linked brcmstb_uart_config
60 sub \tmp, \rp, \rv @ actual brcmstb_uart_config
61 ldr \rp, [\tmp] @ Load brcmstb_uart_config
62 cmp \rp, #1 @ needs initialization?
69 ldr \rp, =ARM_CPU_PART_MASK
70 and \rv, \rv, \rp
71 ldr \rp, =ARM_CPU_PART_BRAHMA_B53 @ check for B53 CPU
72 cmp \rv, \rp
78 ldreq \rp, =SUN_TOP_CTRL_BASE_V7
81 10: ldrne \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA
82 ldr \rv, [\rp, #0] @ get register contents
87 20: checkuart(\rp, \rv, 0x33900000, 3390)
88 21: checkuart(\rp, \rv, 0x72160000, 7216)
89 22: checkuart(\rp, \rv, 0x07216400, 72164)
90 23: checkuart(\rp, \rv, 0x07216500, 72165)
91 24: checkuart(\rp, \rv, 0x72500000, 7250)
92 25: checkuart(\rp, \rv, 0x72550000, 7255)
93 26: checkuart(\rp, \rv, 0x72600000, 7260)
94 27: checkuart(\rp, \rv, 0x72680000, 7268)
95 28: checkuart(\rp, \rv, 0x72710000, 7271)
96 29: checkuart(\rp, \rv, 0x72780000, 7278)
97 30: checkuart(\rp, \rv, 0x73640000, 7364)
98 31: checkuart(\rp, \rv, 0x73660000, 7366)
99 32: checkuart(\rp, \rv, 0x07437100, 74371)
100 33: checkuart(\rp, \rv, 0x74390000, 7439)
101 34: checkuart(\rp, \rv, 0x74450000, 7445)
104 90: mov \rp, #0
108 91: str \rp, [\tmp, #4] @ Store in brcmstb_uart_phys
109 cmp \rp, #0 @ Valid UART address?
111 str \rp, [\tmp, #8] @ Store 0 in brcmstb_uart_virt
113 92: and \rv, \rp, #0xffffff @ offset within 16MB section
124 100: ldr \rp, [\tmp, #4] @ Load brcmstb_uart_phys