Lines Matching defs:mode
57 /* Select code for any configuration running in BE8 mode */
80 * On Feroceon there is much to gain however, regardless of cache mode.
160 * assumes FIQs are enabled, and that the processor is in SVC mode.
304 .macro smp_dmb mode
307 .ifeqs "\mode","arm"
317 .ifeqs "\mode","arm"
327 * setmode is used to assert to be in svc mode during boot. For v7-M
330 .macro setmode, mode, reg
333 .macro setmode, mode, reg
334 mov \reg, #\mode
338 .macro setmode, mode, reg
339 msr cpsr_c, #\mode
344 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
347 * This macro is intended for forcing the CPU into SVC mode at boot time.
348 * you cannot return to the original mode.
526 * above will be 2 bytes when emitting in Thumb mode and 4 bytes when
527 * emitting in ARM mode, so let's use this to account for the bias.