Lines Matching refs:write_aux_reg
281 write_aux_reg(aux_cmd, paddr);
327 write_aux_reg(aux_tag, paddr);
337 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
341 write_aux_reg(aux_tag, paddr);
345 write_aux_reg(aux_cmd, vaddr);
403 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
405 write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);
409 write_aux_reg(aux_cmd, paddr);
449 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
451 write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);
455 write_aux_reg(e, paddr + sz); /* ENDR is exclusive */
456 write_aux_reg(s, paddr);
491 write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH);
515 write_aux_reg(ctl, val);
533 write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH);
554 write_aux_reg(aux, 0x1);
564 write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS);
571 write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS);
611 write_aux_reg(ARC_REG_IC_IVIC, 1);
702 write_aux_reg(ARC_REG_SLC_CTRL, ctrl);
711 write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));
713 write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));
716 write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));
718 write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));
756 write_aux_reg(ARC_REG_SLC_CTRL, ctrl);
766 write_aux_reg(cmd, paddr);
792 write_aux_reg(r, ctrl);
795 write_aux_reg(ARC_REG_SLC_INVALIDATE, 0x1);
797 write_aux_reg(ARC_REG_SLC_FLUSH, 0x1);
811 write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS);
818 write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS);
1193 write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, order_base_2(mem_sz >> 10) - 2);
1201 write_aux_reg(ARC_REG_IO_COH_AP0_BASE, ioc_base >> 12);
1202 write_aux_reg(ARC_REG_IO_COH_PARTIAL, ARC_IO_COH_PARTIAL_BIT);
1203 write_aux_reg(ARC_REG_IO_COH_ENABLE, ARC_IO_COH_ENABLE_BIT);
1320 write_aux_reg(ARC_REG_IC_PTAG_HI, 0);
1323 write_aux_reg(ARC_REG_DC_PTAG_HI, 0);
1326 write_aux_reg(ARC_REG_SLC_RGN_END1, 0);
1327 write_aux_reg(ARC_REG_SLC_RGN_START1, 0);