Lines Matching refs:sz
32 unsigned long sz, const int op, const int full_page);
34 void (*__dma_cache_wback_inv)(phys_addr_t start, unsigned long sz);
35 void (*__dma_cache_inv)(phys_addr_t start, unsigned long sz);
36 void (*__dma_cache_wback)(phys_addr_t start, unsigned long sz);
82 unsigned int pad:24, way:2, lsz:2, sz:4;
84 unsigned int sz:4, lsz:2, way:2, pad:24;
108 p_slc->sz_k = 128 << slc_cfg.sz;
148 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
150 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
168 p_ic->sz_k = 1 << (ibcr.sz - 1);
191 p_dc->sz_k = 1 << (dbcr.sz - 1);
251 unsigned long sz, const int op, const int full_page)
267 * -@sz will be integral multiple of line size (being page sized).
270 sz += paddr & ~CACHE_LINE_MASK;
275 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
296 unsigned long sz, const int op, const int full_page)
313 * -@sz will be integral multiple of line size (being page sized).
316 sz += paddr & ~CACHE_LINE_MASK;
320 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
367 unsigned long sz, const int op, const int full_page)
383 * -@sz will be integral multiple of line size (being page sized).
386 sz += paddr & ~CACHE_LINE_MASK;
390 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
421 unsigned long sz, const int op, const int full_page)
436 sz += paddr & ~CACHE_LINE_MASK;
443 sz += L1_CACHE_BYTES - 1;
455 write_aux_reg(e, paddr + sz); /* ENDR is exclusive */
575 #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
581 unsigned long sz, const int op)
583 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
590 __cache_line_loop(paddr, vaddr, sz, op, full_page);
602 #define __dc_line_op(paddr, vaddr, sz, op)
603 #define __dc_line_op_k(paddr, sz, op)
617 unsigned long sz)
619 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
623 (*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC, full_page);
635 int sz;
642 __ic_line_inv_vaddr_local(ic_inv->paddr, ic_inv->vaddr, ic_inv->sz);
646 unsigned long sz)
651 .sz = sz
662 #define __ic_line_inv_vaddr(pstart, vstart, sz)
666 noinline void slc_op_rgn(phys_addr_t paddr, unsigned long sz, const int op)
707 * END can't be same as START, so add (l2_line_sz - 1) to sz
709 end = paddr + sz + l2_line_sz - 1;
729 noinline void slc_op_line(phys_addr_t paddr, unsigned long sz, const int op)
760 sz += paddr & ~SLC_LINE_MASK;
763 num_lines = DIV_ROUND_UP(sz, l2_line_sz);
779 #define slc_op(paddr, sz, op) slc_op_rgn(paddr, sz, op)
873 static void __dma_cache_wback_inv_l1(phys_addr_t start, unsigned long sz)
875 __dc_line_op_k(start, sz, OP_FLUSH_N_INV);
878 static void __dma_cache_inv_l1(phys_addr_t start, unsigned long sz)
880 __dc_line_op_k(start, sz, OP_INV);
883 static void __dma_cache_wback_l1(phys_addr_t start, unsigned long sz)
885 __dc_line_op_k(start, sz, OP_FLUSH);
892 static void __dma_cache_wback_inv_slc(phys_addr_t start, unsigned long sz)
894 __dc_line_op_k(start, sz, OP_FLUSH_N_INV);
895 slc_op(start, sz, OP_FLUSH_N_INV);
898 static void __dma_cache_inv_slc(phys_addr_t start, unsigned long sz)
900 __dc_line_op_k(start, sz, OP_INV);
901 slc_op(start, sz, OP_INV);
904 static void __dma_cache_wback_slc(phys_addr_t start, unsigned long sz)
906 __dc_line_op_k(start, sz, OP_FLUSH);
907 slc_op(start, sz, OP_FLUSH);
913 void dma_cache_wback_inv(phys_addr_t start, unsigned long sz)
915 __dma_cache_wback_inv(start, sz);
919 void dma_cache_inv(phys_addr_t start, unsigned long sz)
921 __dma_cache_inv(start, sz);
925 void dma_cache_wback(phys_addr_t start, unsigned long sz)
927 __dma_cache_wback(start, sz);
975 unsigned int off, sz;
981 sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off);
982 __sync_icache_dcache(phy, kstart, sz);
983 kstart += sz;
984 tot_sz -= sz;
1132 SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)