Lines Matching defs:r1
24 ; r1 = TLBPD0 from TLB_RELOAD above
31 ; as r0/r1 saves above
37 asr r0,r1,12 ; get set # <<1, note bit 12=R=0
49 /* r1 = data TLBPD0 at this point */
51 xor r0,r0,r1 /* compare set # */
57 ; lr r1,[ARC_REG_TLBPD0] /* Data VPN+ASID - already in r1 from TLB_RELOAD*/
58 and r1,r1,0xff /* Data ASID */
59 or r0,r0,r1 /* Instruction address + Data ASID */
61 lr r1,[ARC_REG_TLBPD0] /* save TLBPD0 containing data TLB*/
65 sr r1,[ARC_REG_TLBPD0] /* restore TLBPD0 */
79 mov_s r3, r1 ; save PD0 prepared by TLB_RELOAD in r3
82 bmsk r1,r3,7 /* Data ASID, bits 7-0 */
83 or_s r0,r0,r1 /* Instruction address + Data ASID */
91 lr r1,[ARC_REG_TLBINDEX] /* r1 = index where MMU wants to put data */
92 cmp r0,r1 /* if no match on indices, go around */
93 xor.eq r1,r1,1 /* flip bottom bit of data index */
94 sr r1,[ARC_REG_TLBINDEX] /* and put it back */