Lines Matching defs:r0
31 ; as r0/r1 saves above
33 ld r0,[jh_ex_way_sel] ; victim pointer
34 and r0,r0,1 ; clean
35 xor.f r0,r0,1 ; flip
36 st r0,[jh_ex_way_sel] ; store back
37 asr r0,r1,12 ; get set # <<1, note bit 12=R=0
38 or.nz r0,r0,1 ; set way bit
39 and r0,r0,0xff ; clean
40 sr r0,[ARC_REG_TLBINDEX]
50 lr r0,[eret] /* instruction address */
51 xor r0,r0,r1 /* compare set # */
52 and.f r0,r0,0x000fe000 /* 2-way MMU mask */
55 lr r0,[eret] /* instruction address */
56 and r0,r0,PAGE_MASK /* VPN of instruction address */
59 or r0,r0,r1 /* Instruction address + Data ASID */
62 sr r0,[ARC_REG_TLBPD0] /* write instruction address to TLBPD0 */
64 lr r0,[ARC_REG_TLBINDEX] /* r0 = index where instruction is, if at all */
67 xor r0,r0,1 /* flip bottom bit of data index */
69 sr r0,[ARC_REG_TLBINDEX] /* and put it back */
80 lr r0,[eret] /* instruction address */
81 and r0,r0,PAGE_MASK /* VPN of instruction address */
83 or_s r0,r0,r1 /* Instruction address + Data ASID */
85 sr r0,[ARC_REG_TLBPD0] /* write instruction address to TLBPD0 */
87 lr r0,[ARC_REG_TLBINDEX] /* r0 = index where instruction is, if at all */
92 cmp r0,r1 /* if no match on indices, go around */