Lines Matching defs:gc
165 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
168 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
176 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
178 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
188 static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
192 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
249 static int rockchip_gpio_direction_input(struct gpio_chip *gc,
252 return rockchip_gpio_set_direction(gc, offset, true);
255 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
258 rockchip_gpio_set(gc, offset, value);
260 return rockchip_gpio_set_direction(gc, offset, false);
268 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
288 rockchip_gpio_set_debounce(gc, offset, debounce);
303 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
305 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
394 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
395 struct rockchip_pin_bank *bank = gc->private;
477 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
478 struct rockchip_pin_bank *bank = gc->private;
480 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
481 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
486 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
487 struct rockchip_pin_bank *bank = gc->private;
489 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
505 struct irq_chip_generic *gc;
527 gc = irq_get_domain_generic_chip(bank->domain, 0);
529 gc->reg_writel = gpio_writel_v2;
530 gc->reg_readl = gpio_readl_v2;
533 gc->reg_base = bank->reg_base;
534 gc->private = bank;
535 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
536 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
537 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
538 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
539 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
540 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
541 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
542 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
543 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
544 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
545 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
546 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
556 gc->mask_cache = 0xffffffff;
566 struct gpio_chip *gc;
571 gc = &bank->gpio_chip;
572 gc->base = bank->pin_base;
573 gc->ngpio = bank->nr_pins;
574 gc->label = bank->name;
575 gc->parent = bank->dev;
577 gc->of_node = of_node_get(bank->of_node);
580 ret = gpiochip_add_data(gc, bank);
583 gc->label, ret);
608 ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0,
609 gc->base, gc->ngpio);