Lines Matching defs:bank
74 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
77 void __iomem *reg = bank->reg_base + offset;
79 if (bank->gpio_type == GPIO_TYPE_V2)
85 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
88 void __iomem *reg = bank->reg_base + offset;
91 if (bank->gpio_type == GPIO_TYPE_V2)
99 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
103 void __iomem *reg = bank->reg_base + offset;
106 if (bank->gpio_type == GPIO_TYPE_V2) {
121 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
124 void __iomem *reg = bank->reg_base + offset;
127 if (bank->gpio_type == GPIO_TYPE_V2) {
141 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
144 data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
154 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
158 raw_spin_lock_irqsave(&bank->slock, flags);
159 rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
160 raw_spin_unlock_irqrestore(&bank->slock, flags);
168 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
171 raw_spin_lock_irqsave(&bank->slock, flags);
172 rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
173 raw_spin_unlock_irqrestore(&bank->slock, flags);
178 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
181 data = readl(bank->reg_base + bank->gpio_regs->ext_port);
192 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
193 const struct rockchip_gpio_regs *reg = bank->gpio_regs;
199 if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
201 freq = clk_get_rate(bank->db_clk);
212 raw_spin_lock_irqsave(&bank->slock, flags);
218 cur_div_reg = readl(bank->reg_base +
221 writel(div_reg, bank->reg_base +
223 rockchip_gpio_writel_bit(bank, offset, 1,
227 rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);
230 rockchip_gpio_writel_bit(bank, offset, 0,
233 rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);
236 raw_spin_unlock_irqrestore(&bank->slock, flags);
241 clk_prepare_enable(bank->db_clk);
243 clk_disable_unprepare(bank->db_clk);
305 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
308 if (!bank->domain)
311 virq = irq_create_mapping(bank->domain, offset);
332 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
335 dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);
339 pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
346 virq = irq_find_mapping(bank->domain, irq);
349 dev_err(bank->dev, "unmapped irq %d\n", irq);
353 dev_dbg(bank->dev, "handling irq %d\n", irq);
359 if (bank->toggle_edge_mode & BIT(irq)) {
363 data = readl_relaxed(bank->reg_base +
364 bank->gpio_regs->ext_port);
366 raw_spin_lock_irqsave(&bank->slock, flags);
368 polarity = readl_relaxed(bank->reg_base +
369 bank->gpio_regs->int_polarity);
375 bank->reg_base +
376 bank->gpio_regs->int_polarity);
378 raw_spin_unlock_irqrestore(&bank->slock, flags);
381 data = readl_relaxed(bank->reg_base +
382 bank->gpio_regs->ext_port);
395 struct rockchip_pin_bank *bank = gc->private;
403 raw_spin_lock_irqsave(&bank->slock, flags);
405 rockchip_gpio_writel_bit(bank, d->hwirq, 0,
406 bank->gpio_regs->port_ddr);
408 raw_spin_unlock_irqrestore(&bank->slock, flags);
415 raw_spin_lock_irqsave(&bank->slock, flags);
417 level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
418 polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
422 if (bank->gpio_type == GPIO_TYPE_V2) {
423 bank->toggle_edge_mode &= ~mask;
424 rockchip_gpio_writel_bit(bank, d->hwirq, 1,
425 bank->gpio_regs->int_bothedge);
428 bank->toggle_edge_mode |= mask;
435 data = readl(bank->reg_base + bank->gpio_regs->ext_port);
443 bank->toggle_edge_mode &= ~mask;
448 bank->toggle_edge_mode &= ~mask;
453 bank->toggle_edge_mode &= ~mask;
458 bank->toggle_edge_mode &= ~mask;
467 rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
468 rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
470 raw_spin_unlock_irqrestore(&bank->slock, flags);
478 struct rockchip_pin_bank *bank = gc->private;
480 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
481 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
487 struct rockchip_pin_bank *bank = gc->private;
489 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
502 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
508 bank->domain = irq_domain_add_linear(bank->of_node, 32,
510 if (!bank->domain) {
511 dev_warn(bank->dev, "could not init irq domain for bank %s\n",
512 bank->name);
516 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
521 dev_err(bank->dev, "could not alloc generic chips for bank %s\n",
522 bank->name);
523 irq_domain_remove(bank->domain);
527 gc = irq_get_domain_generic_chip(bank->domain, 0);
528 if (bank->gpio_type == GPIO_TYPE_V2) {
533 gc->reg_base = bank->reg_base;
534 gc->private = bank;
535 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
536 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
546 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
553 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
554 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi);
555 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
558 irq_set_chained_handler_and_data(bank->irq,
559 rockchip_irq_demux, bank);
564 static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
569 bank->gpio_chip = rockchip_gpiolib_chip;
571 gc = &bank->gpio_chip;
572 gc->base = bank->pin_base;
573 gc->ngpio = bank->nr_pins;
574 gc->label = bank->name;
575 gc->parent = bank->dev;
577 gc->of_node = of_node_get(bank->of_node);
580 ret = gpiochip_add_data(gc, bank);
582 dev_err(bank->dev, "failed to add gpiochip %s, %d\n",
597 if (!of_property_read_bool(bank->of_node, "gpio-ranges")) {
598 struct device_node *pctlnp = of_get_parent(bank->of_node);
611 dev_err(bank->dev, "Failed to add pin range\n");
616 ret = rockchip_interrupts_register(bank);
618 dev_err(bank->dev, "failed to register interrupt, %d\n", ret);
625 gpiochip_remove(&bank->gpio_chip);
630 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
635 if (of_address_to_resource(bank->of_node, 0, &res)) {
636 dev_err(bank->dev, "cannot find IO resource for bank\n");
640 bank->reg_base = devm_ioremap_resource(bank->dev, &res);
641 if (IS_ERR(bank->reg_base))
642 return PTR_ERR(bank->reg_base);
644 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
645 if (!bank->irq)
648 bank->clk = of_clk_get(bank->of_node, 0);
649 if (IS_ERR(bank->clk))
650 return PTR_ERR(bank->clk);
652 clk_prepare_enable(bank->clk);
653 id = readl(bank->reg_base + gpio_regs_v2.version_id);
657 bank->gpio_regs = &gpio_regs_v2;
658 bank->gpio_type = GPIO_TYPE_V2;
659 bank->db_clk = of_clk_get(bank->of_node, 1);
660 if (IS_ERR(bank->db_clk)) {
661 dev_err(bank->dev, "cannot find debounce clk\n");
662 clk_disable_unprepare(bank->clk);
666 bank->gpio_regs = &gpio_regs_v1;
667 bank->gpio_type = GPIO_TYPE_V1;
677 struct rockchip_pin_bank *bank;
681 bank = info->ctrl->pin_banks;
682 for (i = 0; i < info->ctrl->nr_banks; i++, bank++) {
683 if (bank->bank_num == id) {
689 return found ? bank : NULL;
698 struct rockchip_pin_bank *bank = NULL;
714 bank = rockchip_gpio_find_bank(pctldev, id);
715 if (!bank)
718 bank->dev = dev;
719 bank->of_node = np;
721 raw_spin_lock_init(&bank->slock);
723 ret = rockchip_get_bank_data(bank);
731 mutex_lock(&bank->deferred_lock);
733 ret = rockchip_gpiolib_register(bank);
735 clk_disable_unprepare(bank->clk);
736 mutex_unlock(&bank->deferred_lock);
740 while (!list_empty(&bank->deferred_output)) {
741 cfg = list_first_entry(&bank->deferred_output,
745 ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
752 mutex_unlock(&bank->deferred_lock);
754 platform_set_drvdata(pdev, bank);
762 struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
764 clk_disable_unprepare(bank->clk);
765 gpiochip_remove(&bank->gpio_chip);
771 { .compatible = "rockchip,gpio-bank", },