Lines Matching refs:MUX
323 static struct rockchip_clk_branch rk3568_i2s0_8ch_tx_fracmux __initdata = MUX(
326 static struct rockchip_clk_branch rk3568_i2s0_8ch_rx_fracmux __initdata = MUX(
329 static struct rockchip_clk_branch rk3568_i2s1_8ch_tx_fracmux __initdata = MUX(
332 static struct rockchip_clk_branch rk3568_i2s1_8ch_rx_fracmux __initdata = MUX(
336 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(19), 10, 2, MFLAGS);
338 static struct rockchip_clk_branch rk3568_i2s3_2ch_tx_fracmux __initdata = MUX(
341 static struct rockchip_clk_branch rk3568_i2s3_2ch_rx_fracmux __initdata = MUX(
345 MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(23), 15, 1, MFLAGS);
348 MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(25), 15, 1, MFLAGS);
351 MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(52), 12, 2, MFLAGS);
354 MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(54), 12, 2, MFLAGS);
357 MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(56), 12, 2, MFLAGS);
360 MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(58), 12, 2, MFLAGS);
363 MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(60), 12, 2, MFLAGS);
366 MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(62), 12, 2, MFLAGS);
369 MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(64), 12, 2, MFLAGS);
372 MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(66), 12, 2, MFLAGS);
375 MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(68), 12, 2, MFLAGS);
378 MUX(0, "sclk_uart0_mux", sclk_uart0_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
381 MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
427 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, RK3568_MODE_CON0, 14, 2, MFLAGS),
461 MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(6), 11, 1,
475 MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
477 MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(7), 15, 1, MFLAGS),
738 MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK3568_CLKSEL_CON(33), 2,
744 MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", mux_gmac1_rgmii_speed_p, 0, RK3568_CLKSEL_CON(33), 4, 2,
746 MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0, RK3568_CLKSEL_CON(33), 3, 1, MFLAGS),
747 MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(33), 0, 2,
1050 MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0, RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS),
1086 MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0, RK3568_PMU_CLKSEL_CON(8), 0, 1, MFLAGS),
1088 MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0, RK3568_PMU_CLKSEL_CON(8), 1, 1, MFLAGS),
1090 MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0, RK3568_PMU_CLKSEL_CON(8), 2, 1, MFLAGS),
1092 MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0, RK3568_PMU_CLKSEL_CON(8), 3, 1, MFLAGS),
1096 MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS),
1100 MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(9), 3, 1,
1105 MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(9), 7, 1,
1110 MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(9), 11, 1,
1115 MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0, RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS),