Lines Matching refs:GFLAGS
321 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
386 RK3568_CLKGATE_CON(3), 1, GFLAGS);
394 RK3568_CLKGATE_CON(35), 0, GFLAGS),
396 RK3568_CLKGATE_CON(35), 1, GFLAGS),
398 RK3568_CLKGATE_CON(35), 2, GFLAGS),
400 RK3568_CLKGATE_CON(35), 3, GFLAGS),
402 RK3568_CLKGATE_CON(35), 4, GFLAGS),
404 RK3568_CLKGATE_CON(35), 5, GFLAGS),
406 RK3568_CLKGATE_CON(35), 6, GFLAGS),
408 RK3568_CLKGATE_CON(35), 7, GFLAGS),
410 RK3568_CLKGATE_CON(35), 8, GFLAGS),
412 RK3568_CLKGATE_CON(35), 9, GFLAGS),
414 RK3568_CLKGATE_CON(35), 10, GFLAGS),
416 RK3568_CLKGATE_CON(35), 11, GFLAGS),
418 RK3568_CLKGATE_CON(35), 12, GFLAGS),
420 RK3568_CLKGATE_CON(35), 13, GFLAGS),
422 RK3568_CLKGATE_CON(35), 14, GFLAGS),
424 RK3568_CLKGATE_CON(35), 15, GFLAGS),
431 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 5, GFLAGS),
433 RK3568_CLKGATE_CON(0), 7, GFLAGS),
436 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 8, GFLAGS),
438 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 9, GFLAGS),
440 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 10, GFLAGS),
442 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 11, GFLAGS),
444 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 14, GFLAGS),
446 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 15, GFLAGS),
448 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(1), 0, GFLAGS),
451 RK3568_CLKSEL_CON(5), 14, 2, MFLAGS, RK3568_CLKGATE_CON(1), 2, GFLAGS),
453 GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0, RK3568_CLKGATE_CON(1), 10, GFLAGS),
454 GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0, RK3568_CLKGATE_CON(1), 11, GFLAGS),
455 GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(1), 12, GFLAGS),
456 GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0, RK3568_CLKGATE_CON(1), 9, GFLAGS),
460 MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(2), 0, GFLAGS),
465 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0, RK3568_CLKGATE_CON(2), 3, GFLAGS),
467 GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0, RK3568_CLKGATE_CON(2), 6, GFLAGS),
468 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0, RK3568_CLKGATE_CON(2), 7, GFLAGS),
469 GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0, RK3568_CLKGATE_CON(2), 8, GFLAGS),
470 GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(2), 9, GFLAGS),
474 RK3568_CLKGATE_CON(3), 0, GFLAGS, &rk3568_clk_npu_np5),
479 RK3568_CLKGATE_CON(3), 2, GFLAGS),
481 RK3568_CLKGATE_CON(3), 3, GFLAGS),
482 GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0, RK3568_CLKGATE_CON(3), 4, GFLAGS),
483 GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0, RK3568_CLKGATE_CON(3), 7, GFLAGS),
484 GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0, RK3568_CLKGATE_CON(3), 8, GFLAGS),
486 GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0, RK3568_CLKGATE_CON(3), 9, GFLAGS),
487 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0, RK3568_CLKGATE_CON(3), 10, GFLAGS),
488 GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 0, RK3568_CLKGATE_CON(3), 11, GFLAGS),
489 GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(3), 12, GFLAGS),
493 MFLAGS, 0, 5, DFLAGS, RK3568_CLKGATE_CON(4), 0, GFLAGS),
497 RK3568_CLKGATE_CON(4), 2, GFLAGS),
498 GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(4), 15, GFLAGS),
502 RK3568_CLKSEL_CON(10), 8, 2, MFLAGS, RK3568_CLKGATE_CON(5), 0, GFLAGS),
504 RK3568_CLKSEL_CON(10), 10, 2, MFLAGS, RK3568_CLKGATE_CON(5), 1, GFLAGS),
505 GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(5), 8, GFLAGS),
507 MFLAGS, RK3568_CLKGATE_CON(5), 9, GFLAGS),
508 GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(5), 4, GFLAGS),
509 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(5), 7, GFLAGS),
510 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(5), 10, GFLAGS),
511 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(5), 11, GFLAGS),
512 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(5), 12, GFLAGS),
513 GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(5), 13, GFLAGS),
516 7, DFLAGS, RK3568_CLKGATE_CON(6), 0, GFLAGS),
518 RK3568_CLKSEL_CON(12), 0, RK3568_CLKGATE_CON(6), 1, GFLAGS, &rk3568_i2s0_8ch_tx_fracmux,
520 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, RK3568_CLKGATE_CON(6), 2, GFLAGS),
522 15, 1, MFLAGS, RK3568_CLKGATE_CON(6), 3, GFLAGS),
525 7, DFLAGS, RK3568_CLKGATE_CON(6), 4, GFLAGS),
527 RK3568_CLKSEL_CON(14), 0, RK3568_CLKGATE_CON(6), 5, GFLAGS, &rk3568_i2s0_8ch_rx_fracmux,
529 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, RK3568_CLKGATE_CON(6), 6, GFLAGS),
531 15, 1, MFLAGS, RK3568_CLKGATE_CON(6), 7, GFLAGS),
534 7, DFLAGS, RK3568_CLKGATE_CON(6), 8, GFLAGS),
536 RK3568_CLKSEL_CON(16), 0, RK3568_CLKGATE_CON(6), 9, GFLAGS, &rk3568_i2s1_8ch_tx_fracmux,
538 GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, RK3568_CLKGATE_CON(6), 10, GFLAGS),
540 15, 1, MFLAGS, RK3568_CLKGATE_CON(6), 11, GFLAGS),
543 7, DFLAGS, RK3568_CLKGATE_CON(6), 12, GFLAGS),
545 RK3568_CLKSEL_CON(18), 0, RK3568_CLKGATE_CON(6), 13, GFLAGS, &rk3568_i2s1_8ch_rx_fracmux,
547 GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, RK3568_CLKGATE_CON(6), 14, GFLAGS),
549 15, 1, MFLAGS, RK3568_CLKGATE_CON(6), 15, GFLAGS),
552 DFLAGS, RK3568_CLKGATE_CON(7), 0, GFLAGS),
554 RK3568_CLKSEL_CON(20), 0, RK3568_CLKGATE_CON(7), 1, GFLAGS, &rk3568_i2s2_2ch_fracmux,
556 GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, RK3568_CLKGATE_CON(7), 2, GFLAGS),
558 MFLAGS, RK3568_CLKGATE_CON(7), 3, GFLAGS),
561 7, DFLAGS, RK3568_CLKGATE_CON(7), 4, GFLAGS),
563 RK3568_CLKSEL_CON(22), 0, RK3568_CLKGATE_CON(7), 5, GFLAGS, &rk3568_i2s3_2ch_tx_fracmux,
565 GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0, RK3568_CLKGATE_CON(7), 6, GFLAGS),
567 15, 1, MFLAGS, RK3568_CLKGATE_CON(7), 7, GFLAGS),
570 7, DFLAGS, RK3568_CLKGATE_CON(7), 8, GFLAGS),
572 RK3568_CLKSEL_CON(84), 0, RK3568_CLKGATE_CON(7), 9, GFLAGS, &rk3568_i2s3_2ch_rx_fracmux,
574 GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0, RK3568_CLKGATE_CON(7), 10, GFLAGS),
576 15, 1, MFLAGS, RK3568_CLKGATE_CON(7), 11, GFLAGS),
587 GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(5), 14, GFLAGS),
589 GFLAGS),
590 GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(7), 12, GFLAGS),
591 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(7), 13, GFLAGS),
594 DFLAGS, RK3568_CLKGATE_CON(7), 14, GFLAGS),
596 RK3568_CLKSEL_CON(24), 0, RK3568_CLKGATE_CON(7), 15, GFLAGS, &rk3568_spdif_8ch_fracmux,
599 GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(8), 0, GFLAGS),
601 RK3568_CLKGATE_CON(8), 1, GFLAGS),
603 RK3568_CLKSEL_CON(26), 0, RK3568_CLKGATE_CON(8), 2, GFLAGS, &rk3568_audpwm_fracmux,
606 GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(8), 3, GFLAGS),
608 RK3568_CLKGATE_CON(8), 4, GFLAGS),
609 GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 0, RK3568_CLKGATE_CON(8), 5, GFLAGS),
610 GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 0, RK3568_CLKGATE_CON(8), 6, GFLAGS),
614 RK3568_CLKSEL_CON(27), 0, 2, MFLAGS, RK3568_CLKGATE_CON(8), 7, GFLAGS),
616 RK3568_CLKSEL_CON(27), 2, 2, MFLAGS, RK3568_CLKGATE_CON(8), 8, GFLAGS),
617 GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0, RK3568_CLKGATE_CON(8), 11, GFLAGS),
618 GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 0, RK3568_CLKGATE_CON(8), 12, GFLAGS),
620 MFLAGS, RK3568_CLKGATE_CON(8), 13, GFLAGS),
622 MFLAGS, RK3568_CLKGATE_CON(8), 14, GFLAGS),
623 GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 0, RK3568_CLKGATE_CON(8), 15, GFLAGS),
624 GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(9), 10, GFLAGS),
625 GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(9), 11, GFLAGS),
626 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 0, RK3568_CLKGATE_CON(26), 9, GFLAGS),
627 GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0, RK3568_CLKGATE_CON(26), 10, GFLAGS),
628 GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 0, RK3568_CLKGATE_CON(26), 11, GFLAGS),
629 GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0, RK3568_CLKGATE_CON(9), 0, GFLAGS),
631 RK3568_CLKGATE_CON(9), 1, GFLAGS),
632 GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 0, RK3568_CLKGATE_CON(9), 2, GFLAGS),
633 GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 0, RK3568_CLKGATE_CON(9), 3, GFLAGS),
635 GFLAGS),
636 GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 0, RK3568_CLKGATE_CON(9), 5, GFLAGS),
637 GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 0, RK3568_CLKGATE_CON(9), 6, GFLAGS),
639 RK3568_CLKGATE_CON(9), 7, GFLAGS),
641 8, GFLAGS),
642 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, RK3568_CLKGATE_CON(9), 9, GFLAGS),
648 0, GFLAGS),
650 1, GFLAGS),
651 GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 0, RK3568_CLKGATE_CON(12), 0, GFLAGS),
652 GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 0, RK3568_CLKGATE_CON(12), 1, GFLAGS),
653 GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 0, RK3568_CLKGATE_CON(12), 2, GFLAGS),
654 GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 0, RK3568_CLKGATE_CON(12), 3, GFLAGS),
655 GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0, RK3568_CLKGATE_CON(12), 4, GFLAGS),
656 GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0, RK3568_CLKGATE_CON(12), 8, GFLAGS),
657 GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0, RK3568_CLKGATE_CON(12), 9, GFLAGS),
658 GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 0, RK3568_CLKGATE_CON(12), 10, GFLAGS),
659 GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 0, RK3568_CLKGATE_CON(12), 11, GFLAGS),
660 GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0, RK3568_CLKGATE_CON(12), 12, GFLAGS),
661 GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0, RK3568_CLKGATE_CON(13), 0, GFLAGS),
662 GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0, RK3568_CLKGATE_CON(13), 1, GFLAGS),
663 GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 0, RK3568_CLKGATE_CON(13), 2, GFLAGS),
664 GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 0, RK3568_CLKGATE_CON(13), 3, GFLAGS),
665 GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0, RK3568_CLKGATE_CON(13), 4, GFLAGS),
666 GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0, RK3568_CLKGATE_CON(11), 0, GFLAGS),
667 GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0, RK3568_CLKGATE_CON(11), 1, GFLAGS),
668 GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 0, RK3568_CLKGATE_CON(11), 2, GFLAGS),
669 GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 0, RK3568_CLKGATE_CON(11), 4, GFLAGS),
670 GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 0, RK3568_CLKGATE_CON(11), 5, GFLAGS),
671 GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 0, RK3568_CLKGATE_CON(11), 6, GFLAGS),
672 GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 0, RK3568_CLKGATE_CON(11), 8, GFLAGS),
673 GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 0, RK3568_CLKGATE_CON(11), 9, GFLAGS),
674 GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 0, RK3568_CLKGATE_CON(11), 10, GFLAGS),
675 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 0, RK3568_CLKGATE_CON(10), 8, GFLAGS),
676 GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0, RK3568_CLKGATE_CON(10), 9, GFLAGS),
678 RK3568_CLKGATE_CON(10), 10, GFLAGS),
679 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 0, RK3568_CLKGATE_CON(10), 12, GFLAGS),
680 GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0, RK3568_CLKGATE_CON(10), 13, GFLAGS),
682 RK3568_CLKGATE_CON(10), 14, GFLAGS),
684 RK3568_CLKGATE_CON(10), 4, GFLAGS),
685 GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 0, RK3568_CLKGATE_CON(13), 6, GFLAGS),
689 RK3568_CLKGATE_CON(14), 8, GFLAGS),
691 MFLAGS, RK3568_CLKGATE_CON(14), 9, GFLAGS),
693 RK3568_CLKGATE_CON(14), 10, GFLAGS),
694 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0, RK3568_CLKGATE_CON(15), 0, GFLAGS),
696 RK3568_CLKGATE_CON(15), 1, GFLAGS),
700 GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 0, RK3568_CLKGATE_CON(15), 2, GFLAGS),
702 RK3568_CLKGATE_CON(15), 3, GFLAGS),
707 RK3568_CLKGATE_CON(15), 7, GFLAGS),
709 MFLAGS, RK3568_CLKGATE_CON(15), 8, GFLAGS),
710 GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 0, RK3568_CLKGATE_CON(15), 12, GFLAGS),
714 RK3568_CLKGATE_CON(16), 0, GFLAGS),
716 MFLAGS, RK3568_CLKGATE_CON(16), 1, GFLAGS),
718 GFLAGS),
719 GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0, RK3568_CLKGATE_CON(16), 12, GFLAGS),
720 GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 0, RK3568_CLKGATE_CON(16), 13, GFLAGS),
721 GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 0, RK3568_CLKGATE_CON(16), 14, GFLAGS),
722 GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 0, RK3568_CLKGATE_CON(16), 15, GFLAGS),
723 GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 0, RK3568_CLKGATE_CON(17), 0, GFLAGS),
725 RK3568_CLKGATE_CON(17), 1, GFLAGS),
729 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 0, RK3568_CLKGATE_CON(17), 3, GFLAGS),
730 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 0, RK3568_CLKGATE_CON(17), 4, GFLAGS),
732 RK3568_CLKGATE_CON(17), 5, GFLAGS),
734 MFLAGS, RK3568_CLKGATE_CON(17), 6, GFLAGS),
735 GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 0, RK3568_CLKGATE_CON(17), 10, GFLAGS),
737 RK3568_CLKGATE_CON(17), 2, GFLAGS),
752 RK3568_CLKSEL_CON(10), 4, 2, MFLAGS, RK3568_CLKGATE_CON(14), 0, GFLAGS),
754 RK3568_CLKSEL_CON(10), 6, 2, MFLAGS, RK3568_CLKGATE_CON(14), 1, GFLAGS),
758 RK3568_CLKGATE_CON(18), 0, GFLAGS),
760 GFLAGS),
762 GFLAGS),
763 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 0, RK3568_CLKGATE_CON(18), 9, GFLAGS),
764 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0, RK3568_CLKGATE_CON(18), 10, GFLAGS),
766 RK3568_CLKGATE_CON(18), 11, GFLAGS),
767 GATE(ICLK_VICAP_G, "iclk_vicap_g", "iclk_vicap", 0, RK3568_CLKGATE_CON(18), 13, GFLAGS),
768 GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0, RK3568_CLKGATE_CON(19), 0, GFLAGS),
769 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0, RK3568_CLKGATE_CON(19), 1, GFLAGS),
771 RK3568_CLKGATE_CON(19), 2, GFLAGS),
772 GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 0, RK3568_CLKGATE_CON(19), 4, GFLAGS),
774 RK3568_CLKGATE_CON(19), 8, GFLAGS),
776 RK3568_CLKGATE_CON(19), 9, GFLAGS),
778 DFLAGS, RK3568_CLKGATE_CON(19), 10, GFLAGS),
782 RK3568_CLKGATE_CON(20), 0, GFLAGS),
784 GFLAGS),
786 GFLAGS),
788 RK3568_CLKGATE_CON(20), 6, GFLAGS),
789 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK3568_CLKGATE_CON(20), 8, GFLAGS),
790 GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0, RK3568_CLKGATE_CON(20), 9, GFLAGS),
792 RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3568_CLKGATE_CON(20), 10, GFLAGS),
794 RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3568_CLKGATE_CON(20), 11, GFLAGS,
797 RK3568_CLKGATE_CON(20), 12, GFLAGS),
798 GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0, RK3568_CLKGATE_CON(20), 13, GFLAGS),
799 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0, RK3568_CLKGATE_CON(21), 0, GFLAGS),
800 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 0, RK3568_CLKGATE_CON(21), 1, GFLAGS),
801 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 0, RK3568_CLKGATE_CON(21), 2, GFLAGS),
802 GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 0, RK3568_CLKGATE_CON(21), 3, GFLAGS),
803 GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0, RK3568_CLKGATE_CON(21), 4, GFLAGS),
804 GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 0, RK3568_CLKGATE_CON(21), 5, GFLAGS),
805 GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 0, RK3568_CLKGATE_CON(21), 6, GFLAGS),
806 GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 0, RK3568_CLKGATE_CON(21), 7, GFLAGS),
807 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 0, RK3568_CLKGATE_CON(21), 8, GFLAGS),
809 RK3568_CLKGATE_CON(21), 9, GFLAGS),
813 RK3568_CLKGATE_CON(22), 0, GFLAGS),
815 RK3568_CLKGATE_CON(22), 1, GFLAGS),
816 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, RK3568_CLKGATE_CON(22), 4, GFLAGS),
817 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK3568_CLKGATE_CON(22), 5, GFLAGS),
821 MFLAGS, RK3568_CLKGATE_CON(23), 0, GFLAGS),
823 RK3568_CLKGATE_CON(23), 1, GFLAGS),
825 RK3568_CLKGATE_CON(22), 12, GFLAGS),
826 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 4, GFLAGS),
827 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 5, GFLAGS),
829 RK3568_CLKGATE_CON(23), 6, GFLAGS),
830 GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 7, GFLAGS),
831 GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 8, GFLAGS),
833 RK3568_CLKGATE_CON(23), 9, GFLAGS),
834 GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS),
836 RK3568_CLKGATE_CON(23), 11, GFLAGS),
837 GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 12, GFLAGS),
838 GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 13, GFLAGS),
839 GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 14, GFLAGS),
840 GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 15, GFLAGS),
841 GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0, RK3568_CLKGATE_CON(22), 14, GFLAGS),
842 GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(22), 15, GFLAGS),
846 DFLAGS, RK3568_CLKGATE_CON(24), 0, GFLAGS),
848 RK3568_CLKGATE_CON(24), 1, GFLAGS),
849 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0, RK3568_CLKGATE_CON(24), 6, GFLAGS),
850 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0, RK3568_CLKGATE_CON(24), 7, GFLAGS),
852 DFLAGS, RK3568_CLKGATE_CON(24), 8, GFLAGS),
854 1, MFLAGS, 0, 5, DFLAGS, RK3568_CLKGATE_CON(25), 0, GFLAGS),
856 RK3568_CLKGATE_CON(25), 1, GFLAGS),
857 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK3568_CLKGATE_CON(25), 4, GFLAGS),
858 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK3568_CLKGATE_CON(25), 5, GFLAGS),
860 DFLAGS, RK3568_CLKGATE_CON(25), 6, GFLAGS),
862 14, 2, MFLAGS, 8, 5, DFLAGS, RK3568_CLKGATE_CON(25), 7, GFLAGS),
864 0, 5, DFLAGS, RK3568_CLKGATE_CON(25), 8, GFLAGS),
868 2, MFLAGS, RK3568_CLKGATE_CON(26), 0, GFLAGS),
870 MFLAGS, RK3568_CLKGATE_CON(26), 1, GFLAGS),
871 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3568_CLKGATE_CON(26), 4, GFLAGS),
873 DFLAGS, RK3568_CLKGATE_CON(26), 5, GFLAGS),
875 RK3568_CLKGATE_CON(26), 6, GFLAGS),
876 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3568_CLKGATE_CON(26), 7, GFLAGS),
877 GATE(CLK_SARADC, "clk_saradc", "xin24m", 0, RK3568_CLKGATE_CON(26), 8, GFLAGS),
878 GATE(PCLK_SCR, "pclk_scr", "pclk_bus", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(26), 12, GFLAGS),
879 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 0, RK3568_CLKGATE_CON(26), 13, GFLAGS),
880 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0, RK3568_CLKGATE_CON(26), 14, GFLAGS),
881 GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(32), 13, GFLAGS),
882 GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", CLK_IGNORE_UNUSED, RK3568_CLKGATE_CON(32), 14, GFLAGS),
883 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, RK3568_CLKGATE_CON(32), 15, GFLAGS),
885 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3568_CLKGATE_CON(27), 12, GFLAGS),
887 RK3568_CLKGATE_CON(27), 13, GFLAGS),
889 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(27), 14, GFLAGS, &rk3568_uart1_fracmux,
891 GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0, RK3568_CLKGATE_CON(27), 15, GFLAGS),
893 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3568_CLKGATE_CON(28), 0, GFLAGS),
895 RK3568_CLKGATE_CON(28), 1, GFLAGS),
897 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(28), 2, GFLAGS, &rk3568_uart2_fracmux,
899 GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0, RK3568_CLKGATE_CON(28), 3, GFLAGS),
901 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0, RK3568_CLKGATE_CON(28), 4, GFLAGS),
903 RK3568_CLKGATE_CON(28), 5, GFLAGS),
905 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(28), 6, GFLAGS, &rk3568_uart3_fracmux,
907 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0, RK3568_CLKGATE_CON(28), 7, GFLAGS),
909 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0, RK3568_CLKGATE_CON(28), 8, GFLAGS),
911 RK3568_CLKGATE_CON(28), 9, GFLAGS),
913 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(28), 10, GFLAGS, &rk3568_uart4_fracmux,
915 GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0, RK3568_CLKGATE_CON(28), 11, GFLAGS),
917 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0, RK3568_CLKGATE_CON(28), 12, GFLAGS),
919 RK3568_CLKGATE_CON(28), 13, GFLAGS),
921 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(28), 14, GFLAGS, &rk3568_uart5_fracmux,
923 GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0, RK3568_CLKGATE_CON(28), 15, GFLAGS),
925 GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 0, RK3568_CLKGATE_CON(29), 0, GFLAGS),
927 RK3568_CLKGATE_CON(29), 1, GFLAGS),
929 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(29), 2, GFLAGS, &rk3568_uart6_fracmux,
931 GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0, RK3568_CLKGATE_CON(29), 3, GFLAGS),
933 GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0, RK3568_CLKGATE_CON(29), 4, GFLAGS),
935 RK3568_CLKGATE_CON(29), 5, GFLAGS),
937 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(29), 6, GFLAGS, &rk3568_uart7_fracmux,
939 GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0, RK3568_CLKGATE_CON(29), 7, GFLAGS),
941 GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 0, RK3568_CLKGATE_CON(29), 8, GFLAGS),
943 RK3568_CLKGATE_CON(29), 9, GFLAGS),
945 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(29), 10, GFLAGS, &rk3568_uart8_fracmux,
947 GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0, RK3568_CLKGATE_CON(29), 11, GFLAGS),
949 GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 0, RK3568_CLKGATE_CON(29), 12, GFLAGS),
951 RK3568_CLKGATE_CON(29), 13, GFLAGS),
953 CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_CLKGATE_CON(29), 14, GFLAGS, &rk3568_uart9_fracmux,
955 GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0, RK3568_CLKGATE_CON(29), 15, GFLAGS),
957 GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 0, RK3568_CLKGATE_CON(27), 5, GFLAGS),
959 RK3568_CLKGATE_CON(27), 6, GFLAGS),
960 GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 0, RK3568_CLKGATE_CON(27), 7, GFLAGS),
962 RK3568_CLKGATE_CON(27), 8, GFLAGS),
963 GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 0, RK3568_CLKGATE_CON(27), 9, GFLAGS),
965 RK3568_CLKGATE_CON(27), 10, GFLAGS),
967 GFLAGS),
968 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 0, GFLAGS),
969 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0, RK3568_CLKGATE_CON(30), 1, GFLAGS),
970 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 2, GFLAGS),
971 GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0, RK3568_CLKGATE_CON(30), 3, GFLAGS),
972 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 4, GFLAGS),
973 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0, RK3568_CLKGATE_CON(30), 5, GFLAGS),
974 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 6, GFLAGS),
975 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0, RK3568_CLKGATE_CON(30), 7, GFLAGS),
976 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 8, GFLAGS),
977 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0, RK3568_CLKGATE_CON(30), 9, GFLAGS),
978 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 10, GFLAGS),
980 RK3568_CLKGATE_CON(30), 11, GFLAGS),
981 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 12, GFLAGS),
983 RK3568_CLKGATE_CON(30), 13, GFLAGS),
984 GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 14, GFLAGS),
986 RK3568_CLKGATE_CON(30), 15, GFLAGS),
987 GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 0, GFLAGS),
989 RK3568_CLKGATE_CON(31), 1, GFLAGS),
990 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS),
992 RK3568_CLKGATE_CON(31), 11, GFLAGS),
993 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, RK3568_CLKGATE_CON(31), 12, GFLAGS),
994 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 13, GFLAGS),
996 RK3568_CLKGATE_CON(31), 14, GFLAGS),
997 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, RK3568_CLKGATE_CON(31), 15, GFLAGS),
998 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0, RK3568_CLKGATE_CON(32), 0, GFLAGS),
1000 RK3568_CLKGATE_CON(32), 1, GFLAGS),
1001 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, RK3568_CLKGATE_CON(32), 2, GFLAGS),
1003 RK3568_CLKGATE_CON(32), 11, GFLAGS),
1004 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 2, GFLAGS),
1005 GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 0, RK3568_CLKGATE_CON(31), 3, GFLAGS),
1006 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 4, GFLAGS),
1007 GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 0, RK3568_CLKGATE_CON(31), 5, GFLAGS),
1008 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 6, GFLAGS),
1009 GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 0, RK3568_CLKGATE_CON(31), 7, GFLAGS),
1010 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 8, GFLAGS),
1011 GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 0, RK3568_CLKGATE_CON(31), 9, GFLAGS),
1012 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, RK3568_CLKGATE_CON(32), 3, GFLAGS),
1013 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0, RK3568_CLKGATE_CON(32), 4, GFLAGS),
1014 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0, RK3568_CLKGATE_CON(32), 5, GFLAGS),
1015 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0, RK3568_CLKGATE_CON(32), 6, GFLAGS),
1016 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0, RK3568_CLKGATE_CON(32), 7, GFLAGS),
1017 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0, RK3568_CLKGATE_CON(32), 8, GFLAGS),
1018 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0, RK3568_CLKGATE_CON(32), 9, GFLAGS),
1022 RK3568_CLKSEL_CON(73), 0, 2, MFLAGS, RK3568_CLKGATE_CON(33), 0, GFLAGS),
1024 RK3568_CLKSEL_CON(73), 4, 2, MFLAGS, RK3568_CLKGATE_CON(33), 1, GFLAGS),
1026 MFLAGS, RK3568_CLKGATE_CON(33), 2, GFLAGS),
1028 MFLAGS, RK3568_CLKGATE_CON(33), 3, GFLAGS),
1029 GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0, RK3568_CLKGATE_CON(33), 8, GFLAGS),
1031 MFLAGS, RK3568_CLKGATE_CON(33), 9, GFLAGS),
1032 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0, RK3568_CLKGATE_CON(33), 13, GFLAGS),
1033 GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 0, RK3568_CLKGATE_CON(33), 14, GFLAGS),
1034 GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 0, RK3568_CLKGATE_CON(33), 15, GFLAGS),
1035 GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0, RK3568_CLKGATE_CON(34), 4, GFLAGS),
1036 GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 0, RK3568_CLKGATE_CON(34), 5, GFLAGS),
1037 GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 0, RK3568_CLKGATE_CON(34), 6, GFLAGS),
1038 GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 0, RK3568_CLKGATE_CON(34), 11, GFLAGS),
1039 GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0, RK3568_CLKGATE_CON(34), 12, GFLAGS),
1040 GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0, RK3568_CLKGATE_CON(34), 13, GFLAGS),
1041 GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0, RK3568_CLKGATE_CON(34), 14, GFLAGS),
1052 RK3568_PMU_CLKGATE_CON(0), 2, GFLAGS),
1053 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", CLK_IS_CRITICAL, RK3568_PMU_CLKGATE_CON(0), 6, GFLAGS),
1054 GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IS_CRITICAL, RK3568_PMU_CLKGATE_CON(0), 7, GFLAGS),
1055 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0, RK3568_PMU_CLKGATE_CON(1), 0, GFLAGS),
1057 RK3568_PMU_CLKGATE_CON(1), 1, GFLAGS),
1058 GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0, RK3568_PMU_CLKGATE_CON(1), 2, GFLAGS),
1061 RK3568_PMU_CLKGATE_CON(0), 1, GFLAGS, &rk3568_rtc32k_pmu_fracmux, 0),
1064 RK3568_PMU_CLKGATE_CON(0), 0, GFLAGS),
1067 7, DFLAGS, RK3568_PMU_CLKGATE_CON(1), 3, GFLAGS),
1069 RK3568_PMU_CLKSEL_CON(5), CLK_FRAC_DIVIDER_NO_LIMIT, RK3568_PMU_CLKGATE_CON(1), 4, GFLAGS,
1071 GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0, RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS),
1073 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0, RK3568_PMU_CLKGATE_CON(1), 9, GFLAGS),
1075 RK3568_PMU_CLKGATE_CON(1), 10, GFLAGS),
1076 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0, RK3568_PMU_CLKGATE_CON(1), 6, GFLAGS),
1078 RK3568_PMU_CLKGATE_CON(1), 7, GFLAGS),
1079 GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0, RK3568_PMU_CLKGATE_CON(1), 8, GFLAGS),
1080 GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0, RK3568_PMU_CLKGATE_CON(1), 11, GFLAGS),
1081 GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0, RK3568_PMU_CLKGATE_CON(1), 12, GFLAGS),
1082 GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0, RK3568_PMU_CLKGATE_CON(1), 13, GFLAGS),
1084 RK3568_PMU_CLKGATE_CON(2), 0, GFLAGS),
1085 GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 1, GFLAGS),
1087 GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 2, GFLAGS),
1089 GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 3, GFLAGS),
1091 GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 4, GFLAGS),
1094 RK3568_PMU_CLKGATE_CON(2), 5, GFLAGS),
1095 GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 6, GFLAGS),
1098 RK3568_PMU_CLKGATE_CON(2), 7, GFLAGS),
1099 GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 8, GFLAGS),
1103 RK3568_PMU_CLKGATE_CON(2), 9, GFLAGS),
1104 GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 10, GFLAGS),
1108 RK3568_PMU_CLKGATE_CON(2), 11, GFLAGS),
1109 GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 12, GFLAGS),
1112 GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0, RK3568_PMU_CLKGATE_CON(2), 13, GFLAGS),
1113 GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 0, RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS),
1114 GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS),