Lines Matching defs:lane
304 * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
308 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
312 * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
316 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
501 prop = of_find_property(np, "rockchip,dp-lane-mux", &len);
503 dev_dbg(udphy->dev, "failed to find dp lane mux, following dp alt mode\n");
511 dev_err(udphy->dev, "invalid number of lane mux\n");
515 ret = of_property_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes);
517 dev_err(udphy->dev, "get dp lane mux failed\n");
525 dev_err(udphy->dev, "lane mux between 0 and 3, exceeding the range\n");
533 dev_err(udphy->dev, "set repeat lane mux value\n");
744 /* Verify lane count. */
749 /* valid lane count. */
757 * levels, per-lane.
1133 /* Step 3: configure lane mux */
1152 /* Step 5: deassert cmn/lane rstn */
1155 udphy_reset_deassert(udphy, "lane");
1169 udphy_reset_assert(udphy, "lane");
1293 static void rk3588_dp_phy_set_voltage(struct rockchip_udphy *udphy, u32 voltage, u32 pre, u32 lane)
1295 u32 offset = 0x800 * lane;
1313 u32 i, lane;
1316 lane = udphy->dp_lane_sel[i];
1320 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), LN_ANA_TX_SER_TXCLK_INV,
1321 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, udphy->lane_mux_sel[lane]));
1325 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), LN_ANA_TX_SER_TXCLK_INV,
1330 rk3588_dp_phy_set_voltage(udphy, dp->voltage[i], dp->pre[i], lane);
1336 static const char *const rk3588_udphy_rst_l[] = {"init", "cmn", "lane", "pcs_apb", "pma_apb"};